nVMX: Extend EPT cap MSR test to allow 5-level EPT
Modify the EMSR_IA32_VMX_EPT_VPID_CAP test to mark the 5-level EPT cap
bit as allowed-1. KVM is in the process of gaining support for 5-level
nested EPT[*].
[*] https://lkml.kernel.org/r/20200206220836.22743-1-sean.j.christopherson@intel.com
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Message-Id: <20200207174244.6590-5-sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
diff --git a/x86/vmx.c b/x86/vmx.c
index b3d6dc6..07415b4 100644
--- a/x86/vmx.c
+++ b/x86/vmx.c
@@ -1677,6 +1677,7 @@
fixed0 = -1ull;
fixed0 &= ~(EPT_CAP_WT |
EPT_CAP_PWL4 |
+ EPT_CAP_PWL5 |
EPT_CAP_UC |
EPT_CAP_WB |
EPT_CAP_2M_PAGE |
