| if (this_cpu_has(X86_FEATURE_TSC_ADJUST)) { // MSR_IA32_TSC_ADJUST Feature is enabled? |
| report(rdmsr(MSR_IA32_TSC_ADJUST) == 0x0, |
| "MSR_IA32_TSC_ADJUST msr initialization"); |
| wrmsr(MSR_IA32_TSC_ADJUST, t3); |
| report(rdmsr(MSR_IA32_TSC_ADJUST) == t3, |
| "MSR_IA32_TSC_ADJUST msr read / write"); |
| "TSC adjustment for MSR_IA32_TSC_ADJUST value"); |
| wrmsr(MSR_IA32_TSC_ADJUST, t3); |
| report(rdmsr(MSR_IA32_TSC_ADJUST) == t3, |
| "MSR_IA32_TSC_ADJUST msr read / write"); |
| t5 = rdmsr(MSR_IA32_TSC_ADJUST); |
| // est of time between reading tsc and writing tsc, |
| // (based on MSR_IA32_TSC_ADJUST msr value) should be small |
| est_delta_time = t4 - t5 - t1; |
| // arbitray 2x latency (wrtsc->rdtsc) threshold |
| report(est_delta_time <= (2 * (t2 - t4)), |
| "MSR_IA32_TSC_ADJUST msr adjustment on tsc write"); |
| report_pass("MSR_IA32_TSC_ADJUST feature not enabled"); |