Cornelia Huck | c865f65 | 2021-06-09 16:37:12 +0200 | [diff] [blame] | 1 | #ifndef X86_SVM_H |
| 2 | #define X86_SVM_H |
Avi Kivity | 7d36db3 | 2010-08-03 14:07:34 +0300 | [diff] [blame] | 3 | |
| 4 | #include "libcflat.h" |
| 5 | |
| 6 | enum { |
| 7 | INTERCEPT_INTR, |
| 8 | INTERCEPT_NMI, |
| 9 | INTERCEPT_SMI, |
| 10 | INTERCEPT_INIT, |
| 11 | INTERCEPT_VINTR, |
| 12 | INTERCEPT_SELECTIVE_CR0, |
| 13 | INTERCEPT_STORE_IDTR, |
| 14 | INTERCEPT_STORE_GDTR, |
| 15 | INTERCEPT_STORE_LDTR, |
| 16 | INTERCEPT_STORE_TR, |
| 17 | INTERCEPT_LOAD_IDTR, |
| 18 | INTERCEPT_LOAD_GDTR, |
| 19 | INTERCEPT_LOAD_LDTR, |
| 20 | INTERCEPT_LOAD_TR, |
| 21 | INTERCEPT_RDTSC, |
| 22 | INTERCEPT_RDPMC, |
| 23 | INTERCEPT_PUSHF, |
| 24 | INTERCEPT_POPF, |
| 25 | INTERCEPT_CPUID, |
| 26 | INTERCEPT_RSM, |
| 27 | INTERCEPT_IRET, |
| 28 | INTERCEPT_INTn, |
| 29 | INTERCEPT_INVD, |
| 30 | INTERCEPT_PAUSE, |
| 31 | INTERCEPT_HLT, |
| 32 | INTERCEPT_INVLPG, |
| 33 | INTERCEPT_INVLPGA, |
| 34 | INTERCEPT_IOIO_PROT, |
| 35 | INTERCEPT_MSR_PROT, |
| 36 | INTERCEPT_TASK_SWITCH, |
| 37 | INTERCEPT_FERR_FREEZE, |
| 38 | INTERCEPT_SHUTDOWN, |
| 39 | INTERCEPT_VMRUN, |
| 40 | INTERCEPT_VMMCALL, |
| 41 | INTERCEPT_VMLOAD, |
| 42 | INTERCEPT_VMSAVE, |
| 43 | INTERCEPT_STGI, |
| 44 | INTERCEPT_CLGI, |
| 45 | INTERCEPT_SKINIT, |
| 46 | INTERCEPT_RDTSCP, |
| 47 | INTERCEPT_ICEBP, |
| 48 | INTERCEPT_WBINVD, |
| 49 | INTERCEPT_MONITOR, |
| 50 | INTERCEPT_MWAIT, |
| 51 | INTERCEPT_MWAIT_COND, |
| 52 | }; |
| 53 | |
Paolo Bonzini | f7fa53d | 2021-02-26 12:01:23 -0500 | [diff] [blame] | 54 | enum { |
| 55 | VMCB_CLEAN_INTERCEPTS = 1, /* Intercept vectors, TSC offset, pause filter count */ |
| 56 | VMCB_CLEAN_PERM_MAP = 2, /* IOPM Base and MSRPM Base */ |
| 57 | VMCB_CLEAN_ASID = 4, /* ASID */ |
| 58 | VMCB_CLEAN_INTR = 8, /* int_ctl, int_vector */ |
| 59 | VMCB_CLEAN_NPT = 16, /* npt_en, nCR3, gPAT */ |
| 60 | VMCB_CLEAN_CR = 32, /* CR0, CR3, CR4, EFER */ |
| 61 | VMCB_CLEAN_DR = 64, /* DR6, DR7 */ |
| 62 | VMCB_CLEAN_DT = 128, /* GDT, IDT */ |
| 63 | VMCB_CLEAN_SEG = 256, /* CS, DS, SS, ES, CPL */ |
| 64 | VMCB_CLEAN_CR2 = 512, /* CR2 only */ |
| 65 | VMCB_CLEAN_LBR = 1024, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ |
| 66 | VMCB_CLEAN_AVIC = 2048, /* APIC_BAR, APIC_BACKING_PAGE, |
| 67 | PHYSICAL_TABLE pointer, LOGICAL_TABLE pointer */ |
| 68 | VMCB_CLEAN_ALL = 4095, |
| 69 | }; |
Avi Kivity | 7d36db3 | 2010-08-03 14:07:34 +0300 | [diff] [blame] | 70 | |
| 71 | struct __attribute__ ((__packed__)) vmcb_control_area { |
| 72 | u16 intercept_cr_read; |
| 73 | u16 intercept_cr_write; |
| 74 | u16 intercept_dr_read; |
| 75 | u16 intercept_dr_write; |
| 76 | u32 intercept_exceptions; |
| 77 | u64 intercept; |
| 78 | u8 reserved_1[42]; |
| 79 | u16 pause_filter_count; |
| 80 | u64 iopm_base_pa; |
| 81 | u64 msrpm_base_pa; |
| 82 | u64 tsc_offset; |
| 83 | u32 asid; |
| 84 | u8 tlb_ctl; |
| 85 | u8 reserved_2[3]; |
| 86 | u32 int_ctl; |
| 87 | u32 int_vector; |
| 88 | u32 int_state; |
| 89 | u8 reserved_3[4]; |
| 90 | u32 exit_code; |
| 91 | u32 exit_code_hi; |
| 92 | u64 exit_info_1; |
| 93 | u64 exit_info_2; |
| 94 | u32 exit_int_info; |
| 95 | u32 exit_int_info_err; |
| 96 | u64 nested_ctl; |
| 97 | u8 reserved_4[16]; |
| 98 | u32 event_inj; |
| 99 | u32 event_inj_err; |
| 100 | u64 nested_cr3; |
| 101 | u64 lbr_ctl; |
Paolo Bonzini | f7fa53d | 2021-02-26 12:01:23 -0500 | [diff] [blame] | 102 | u32 clean; |
| 103 | u32 reserved_5; |
Avi Kivity | 7d36db3 | 2010-08-03 14:07:34 +0300 | [diff] [blame] | 104 | u64 next_rip; |
Paolo Bonzini | f7fa53d | 2021-02-26 12:01:23 -0500 | [diff] [blame] | 105 | u8 insn_len; |
| 106 | u8 insn_bytes[15]; |
| 107 | u8 reserved_6[800]; |
Avi Kivity | 7d36db3 | 2010-08-03 14:07:34 +0300 | [diff] [blame] | 108 | }; |
| 109 | |
Avi Kivity | 7d36db3 | 2010-08-03 14:07:34 +0300 | [diff] [blame] | 110 | #define TLB_CONTROL_DO_NOTHING 0 |
| 111 | #define TLB_CONTROL_FLUSH_ALL_ASID 1 |
| 112 | |
| 113 | #define V_TPR_MASK 0x0f |
| 114 | |
| 115 | #define V_IRQ_SHIFT 8 |
| 116 | #define V_IRQ_MASK (1 << V_IRQ_SHIFT) |
| 117 | |
| 118 | #define V_INTR_PRIO_SHIFT 16 |
| 119 | #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) |
| 120 | |
| 121 | #define V_IGN_TPR_SHIFT 20 |
| 122 | #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) |
| 123 | |
| 124 | #define V_INTR_MASKING_SHIFT 24 |
| 125 | #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) |
| 126 | |
| 127 | #define SVM_INTERRUPT_SHADOW_MASK 1 |
| 128 | |
| 129 | #define SVM_IOIO_STR_SHIFT 2 |
| 130 | #define SVM_IOIO_REP_SHIFT 3 |
| 131 | #define SVM_IOIO_SIZE_SHIFT 4 |
| 132 | #define SVM_IOIO_ASIZE_SHIFT 7 |
| 133 | |
| 134 | #define SVM_IOIO_TYPE_MASK 1 |
| 135 | #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) |
| 136 | #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) |
| 137 | #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) |
| 138 | #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) |
| 139 | |
| 140 | #define SVM_VM_CR_VALID_MASK 0x001fULL |
| 141 | #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL |
| 142 | #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL |
| 143 | |
| 144 | struct __attribute__ ((__packed__)) vmcb_seg { |
| 145 | u16 selector; |
| 146 | u16 attrib; |
| 147 | u32 limit; |
| 148 | u64 base; |
| 149 | }; |
| 150 | |
| 151 | struct __attribute__ ((__packed__)) vmcb_save_area { |
| 152 | struct vmcb_seg es; |
| 153 | struct vmcb_seg cs; |
| 154 | struct vmcb_seg ss; |
| 155 | struct vmcb_seg ds; |
| 156 | struct vmcb_seg fs; |
| 157 | struct vmcb_seg gs; |
| 158 | struct vmcb_seg gdtr; |
| 159 | struct vmcb_seg ldtr; |
| 160 | struct vmcb_seg idtr; |
| 161 | struct vmcb_seg tr; |
| 162 | u8 reserved_1[43]; |
| 163 | u8 cpl; |
| 164 | u8 reserved_2[4]; |
| 165 | u64 efer; |
| 166 | u8 reserved_3[112]; |
| 167 | u64 cr4; |
| 168 | u64 cr3; |
| 169 | u64 cr0; |
| 170 | u64 dr7; |
| 171 | u64 dr6; |
| 172 | u64 rflags; |
| 173 | u64 rip; |
| 174 | u8 reserved_4[88]; |
| 175 | u64 rsp; |
| 176 | u8 reserved_5[24]; |
| 177 | u64 rax; |
| 178 | u64 star; |
| 179 | u64 lstar; |
| 180 | u64 cstar; |
| 181 | u64 sfmask; |
| 182 | u64 kernel_gs_base; |
| 183 | u64 sysenter_cs; |
| 184 | u64 sysenter_esp; |
| 185 | u64 sysenter_eip; |
| 186 | u64 cr2; |
| 187 | u8 reserved_6[32]; |
| 188 | u64 g_pat; |
| 189 | u64 dbgctl; |
| 190 | u64 br_from; |
| 191 | u64 br_to; |
| 192 | u64 last_excp_from; |
| 193 | u64 last_excp_to; |
| 194 | }; |
| 195 | |
| 196 | struct __attribute__ ((__packed__)) vmcb { |
| 197 | struct vmcb_control_area control; |
| 198 | struct vmcb_save_area save; |
| 199 | }; |
| 200 | |
| 201 | #define SVM_CPUID_FEATURE_SHIFT 2 |
| 202 | #define SVM_CPUID_FUNC 0x8000000a |
| 203 | |
| 204 | #define SVM_VM_CR_SVM_DISABLE 4 |
| 205 | |
| 206 | #define SVM_SELECTOR_S_SHIFT 4 |
| 207 | #define SVM_SELECTOR_DPL_SHIFT 5 |
| 208 | #define SVM_SELECTOR_P_SHIFT 7 |
| 209 | #define SVM_SELECTOR_AVL_SHIFT 8 |
| 210 | #define SVM_SELECTOR_L_SHIFT 9 |
| 211 | #define SVM_SELECTOR_DB_SHIFT 10 |
| 212 | #define SVM_SELECTOR_G_SHIFT 11 |
| 213 | |
| 214 | #define SVM_SELECTOR_TYPE_MASK (0xf) |
| 215 | #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) |
| 216 | #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) |
| 217 | #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) |
| 218 | #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) |
| 219 | #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) |
| 220 | #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) |
| 221 | #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) |
| 222 | |
| 223 | #define SVM_SELECTOR_WRITE_MASK (1 << 1) |
| 224 | #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK |
| 225 | #define SVM_SELECTOR_CODE_MASK (1 << 3) |
| 226 | |
| 227 | #define INTERCEPT_CR0_MASK 1 |
| 228 | #define INTERCEPT_CR3_MASK (1 << 3) |
| 229 | #define INTERCEPT_CR4_MASK (1 << 4) |
| 230 | #define INTERCEPT_CR8_MASK (1 << 8) |
| 231 | |
| 232 | #define INTERCEPT_DR0_MASK 1 |
| 233 | #define INTERCEPT_DR1_MASK (1 << 1) |
| 234 | #define INTERCEPT_DR2_MASK (1 << 2) |
| 235 | #define INTERCEPT_DR3_MASK (1 << 3) |
| 236 | #define INTERCEPT_DR4_MASK (1 << 4) |
| 237 | #define INTERCEPT_DR5_MASK (1 << 5) |
| 238 | #define INTERCEPT_DR6_MASK (1 << 6) |
| 239 | #define INTERCEPT_DR7_MASK (1 << 7) |
| 240 | |
| 241 | #define SVM_EVTINJ_VEC_MASK 0xff |
| 242 | |
| 243 | #define SVM_EVTINJ_TYPE_SHIFT 8 |
| 244 | #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) |
| 245 | |
| 246 | #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) |
| 247 | #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) |
| 248 | #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) |
| 249 | #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) |
| 250 | |
| 251 | #define SVM_EVTINJ_VALID (1 << 31) |
| 252 | #define SVM_EVTINJ_VALID_ERR (1 << 11) |
| 253 | |
| 254 | #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK |
| 255 | #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK |
| 256 | |
| 257 | #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR |
| 258 | #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI |
| 259 | #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT |
| 260 | #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT |
| 261 | |
| 262 | #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID |
| 263 | #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR |
| 264 | |
| 265 | #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 |
| 266 | #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 |
| 267 | #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 |
| 268 | |
| 269 | #define SVM_EXIT_READ_CR0 0x000 |
| 270 | #define SVM_EXIT_READ_CR3 0x003 |
| 271 | #define SVM_EXIT_READ_CR4 0x004 |
| 272 | #define SVM_EXIT_READ_CR8 0x008 |
| 273 | #define SVM_EXIT_WRITE_CR0 0x010 |
| 274 | #define SVM_EXIT_WRITE_CR3 0x013 |
| 275 | #define SVM_EXIT_WRITE_CR4 0x014 |
| 276 | #define SVM_EXIT_WRITE_CR8 0x018 |
| 277 | #define SVM_EXIT_READ_DR0 0x020 |
| 278 | #define SVM_EXIT_READ_DR1 0x021 |
| 279 | #define SVM_EXIT_READ_DR2 0x022 |
| 280 | #define SVM_EXIT_READ_DR3 0x023 |
| 281 | #define SVM_EXIT_READ_DR4 0x024 |
| 282 | #define SVM_EXIT_READ_DR5 0x025 |
| 283 | #define SVM_EXIT_READ_DR6 0x026 |
| 284 | #define SVM_EXIT_READ_DR7 0x027 |
| 285 | #define SVM_EXIT_WRITE_DR0 0x030 |
| 286 | #define SVM_EXIT_WRITE_DR1 0x031 |
| 287 | #define SVM_EXIT_WRITE_DR2 0x032 |
| 288 | #define SVM_EXIT_WRITE_DR3 0x033 |
| 289 | #define SVM_EXIT_WRITE_DR4 0x034 |
| 290 | #define SVM_EXIT_WRITE_DR5 0x035 |
| 291 | #define SVM_EXIT_WRITE_DR6 0x036 |
| 292 | #define SVM_EXIT_WRITE_DR7 0x037 |
| 293 | #define SVM_EXIT_EXCP_BASE 0x040 |
| 294 | #define SVM_EXIT_INTR 0x060 |
| 295 | #define SVM_EXIT_NMI 0x061 |
| 296 | #define SVM_EXIT_SMI 0x062 |
| 297 | #define SVM_EXIT_INIT 0x063 |
| 298 | #define SVM_EXIT_VINTR 0x064 |
| 299 | #define SVM_EXIT_CR0_SEL_WRITE 0x065 |
| 300 | #define SVM_EXIT_IDTR_READ 0x066 |
| 301 | #define SVM_EXIT_GDTR_READ 0x067 |
| 302 | #define SVM_EXIT_LDTR_READ 0x068 |
| 303 | #define SVM_EXIT_TR_READ 0x069 |
| 304 | #define SVM_EXIT_IDTR_WRITE 0x06a |
| 305 | #define SVM_EXIT_GDTR_WRITE 0x06b |
| 306 | #define SVM_EXIT_LDTR_WRITE 0x06c |
| 307 | #define SVM_EXIT_TR_WRITE 0x06d |
| 308 | #define SVM_EXIT_RDTSC 0x06e |
| 309 | #define SVM_EXIT_RDPMC 0x06f |
| 310 | #define SVM_EXIT_PUSHF 0x070 |
| 311 | #define SVM_EXIT_POPF 0x071 |
| 312 | #define SVM_EXIT_CPUID 0x072 |
| 313 | #define SVM_EXIT_RSM 0x073 |
| 314 | #define SVM_EXIT_IRET 0x074 |
| 315 | #define SVM_EXIT_SWINT 0x075 |
| 316 | #define SVM_EXIT_INVD 0x076 |
| 317 | #define SVM_EXIT_PAUSE 0x077 |
| 318 | #define SVM_EXIT_HLT 0x078 |
| 319 | #define SVM_EXIT_INVLPG 0x079 |
| 320 | #define SVM_EXIT_INVLPGA 0x07a |
| 321 | #define SVM_EXIT_IOIO 0x07b |
| 322 | #define SVM_EXIT_MSR 0x07c |
| 323 | #define SVM_EXIT_TASK_SWITCH 0x07d |
| 324 | #define SVM_EXIT_FERR_FREEZE 0x07e |
| 325 | #define SVM_EXIT_SHUTDOWN 0x07f |
| 326 | #define SVM_EXIT_VMRUN 0x080 |
| 327 | #define SVM_EXIT_VMMCALL 0x081 |
| 328 | #define SVM_EXIT_VMLOAD 0x082 |
| 329 | #define SVM_EXIT_VMSAVE 0x083 |
| 330 | #define SVM_EXIT_STGI 0x084 |
| 331 | #define SVM_EXIT_CLGI 0x085 |
| 332 | #define SVM_EXIT_SKINIT 0x086 |
| 333 | #define SVM_EXIT_RDTSCP 0x087 |
| 334 | #define SVM_EXIT_ICEBP 0x088 |
| 335 | #define SVM_EXIT_WBINVD 0x089 |
| 336 | #define SVM_EXIT_MONITOR 0x08a |
| 337 | #define SVM_EXIT_MWAIT 0x08b |
| 338 | #define SVM_EXIT_MWAIT_COND 0x08c |
| 339 | #define SVM_EXIT_NPF 0x400 |
| 340 | |
| 341 | #define SVM_EXIT_ERR -1 |
| 342 | |
| 343 | #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) |
| 344 | |
Krish Sadhukhan | eae10e8 | 2020-05-22 18:19:53 -0400 | [diff] [blame] | 345 | #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U |
Krish Sadhukhan | 6d0ecbf | 2020-10-06 19:06:53 +0000 | [diff] [blame] | 346 | #define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U |
| 347 | #define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U |
| 348 | #define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U |
Krish Sadhukhan | a79c949 | 2020-07-08 00:39:57 +0000 | [diff] [blame] | 349 | #define SVM_CR4_LEGACY_RESERVED_MASK 0xff88f000U |
| 350 | #define SVM_CR4_RESERVED_MASK 0xffffffffff88f000U |
Krish Sadhukhan | eae10e8 | 2020-05-22 18:19:53 -0400 | [diff] [blame] | 351 | #define SVM_DR6_RESERVED_MASK 0xffffffffffff1ff0U |
| 352 | #define SVM_DR7_RESERVED_MASK 0xffffffff0000cc00U |
| 353 | #define SVM_EFER_RESERVED_MASK 0xffffffffffff0200U |
| 354 | |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 355 | #define MSR_BITMAP_SIZE 8192 |
Avi Kivity | 7d36db3 | 2010-08-03 14:07:34 +0300 | [diff] [blame] | 356 | |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 357 | struct svm_test { |
| 358 | const char *name; |
| 359 | bool (*supported)(void); |
| 360 | void (*prepare)(struct svm_test *test); |
| 361 | void (*prepare_gif_clear)(struct svm_test *test); |
| 362 | void (*guest_func)(struct svm_test *test); |
| 363 | bool (*finished)(struct svm_test *test); |
| 364 | bool (*succeeded)(struct svm_test *test); |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 365 | int exits; |
| 366 | ulong scratch; |
Krish Sadhukhan | 8660d1b | 2020-03-17 13:05:35 -0700 | [diff] [blame] | 367 | /* Alternative test interface. */ |
| 368 | void (*v2)(void); |
Cathy Avery | 48f6791 | 2020-07-17 07:34:20 -0400 | [diff] [blame] | 369 | int on_vcpu; |
| 370 | bool on_vcpu_done; |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 371 | }; |
| 372 | |
| 373 | struct regs { |
| 374 | u64 rax; |
| 375 | u64 rbx; |
| 376 | u64 rcx; |
| 377 | u64 rdx; |
| 378 | u64 cr2; |
| 379 | u64 rbp; |
| 380 | u64 rsi; |
| 381 | u64 rdi; |
| 382 | u64 r8; |
| 383 | u64 r9; |
| 384 | u64 r10; |
| 385 | u64 r11; |
| 386 | u64 r12; |
| 387 | u64 r13; |
| 388 | u64 r14; |
| 389 | u64 r15; |
| 390 | u64 rflags; |
| 391 | }; |
| 392 | |
Krish Sadhukhan | 8660d1b | 2020-03-17 13:05:35 -0700 | [diff] [blame] | 393 | typedef void (*test_guest_func)(struct svm_test *); |
| 394 | |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 395 | u64 *npt_get_pte(u64 address); |
| 396 | u64 *npt_get_pde(u64 address); |
| 397 | u64 *npt_get_pdpe(void); |
Nadav Amit | c6405e3 | 2020-06-30 02:45:15 -0700 | [diff] [blame] | 398 | u64 *npt_get_pml4e(void); |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 399 | bool smp_supported(void); |
| 400 | bool default_supported(void); |
| 401 | void default_prepare(struct svm_test *test); |
| 402 | void default_prepare_gif_clear(struct svm_test *test); |
| 403 | bool default_finished(struct svm_test *test); |
| 404 | bool npt_supported(void); |
| 405 | int get_test_stage(struct svm_test *test); |
| 406 | void set_test_stage(struct svm_test *test, int s); |
| 407 | void inc_test_stage(struct svm_test *test); |
| 408 | void vmcb_ident(struct vmcb *vmcb); |
| 409 | struct regs get_regs(void); |
| 410 | void vmmcall(void); |
Krish Sadhukhan | 8660d1b | 2020-03-17 13:05:35 -0700 | [diff] [blame] | 411 | int svm_vmrun(void); |
| 412 | void test_set_guest(test_guest_func func); |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 413 | |
Paolo Bonzini | 096cf7f | 2020-03-18 13:15:36 +0100 | [diff] [blame] | 414 | extern struct vmcb *vmcb; |
| 415 | extern struct svm_test svm_tests[]; |
| 416 | |
Krish Sadhukhan | ad87912 | 2020-02-05 15:50:26 -0500 | [diff] [blame] | 417 | #endif |