pci: Limit configuration transaction size to 32 bits
>From PCI Local Bus Specification Revision 3.0. section 3.8 "64-Bit Bus
Extension":
"The bandwidth requirements for I/O and configuration transactions cannot
justify the added complexity, and, therefore, only memory transactions
support 64-bit data transfers".
Further down, the spec also describes the possible responses of a target
which has been requested to do a 64-bit transaction. Limit the transaction
to the lower 32 bits, to match the second accepted behaviour.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/1589470709-4104-6-git-send-email-alexandru.elisei@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
diff --git a/pci.c b/pci.c
index 81e9cec..eb0bb36 100644
--- a/pci.c
+++ b/pci.c
@@ -119,6 +119,9 @@
{
union pci_config_address pci_config_address;
+ if (size > 4)
+ size = 4;
+
pci_config_address.w = ioport__read32(&pci_config_address_bits);
/*
* If someone accesses PCI configuration space offsets that are not
@@ -135,6 +138,9 @@
{
union pci_config_address pci_config_address;
+ if (size > 4)
+ size = 4;
+
pci_config_address.w = ioport__read32(&pci_config_address_bits);
/*
* If someone accesses PCI configuration space offsets that are not
@@ -248,6 +254,9 @@
cfg_addr.w = (u32)addr;
cfg_addr.enable_bit = 1;
+ if (len > 4)
+ len = 4;
+
if (is_write)
pci__config_wr(kvm, cfg_addr, data, len);
else
