arch/arm64/boot/dts/ti/k3-am62p.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for AM62P SoC Family
 *
 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>

#include "k3-pinctrl.h"

/ {
	model = "Texas Instruments K3 AM62P5 SoC";
	compatible = "ti,am62p5";
	interrupt-parent = <&gic500>;
	#address-cells = <2>;
	#size-cells = <2>;

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci: psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	a53_timer0: timer-cl0-cpu0 {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	cbass_main: bus@f0000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		bootph-all;

		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */

			 /* MCU Domain Range */
			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
			 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
			 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
			 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
			 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,

			 /* Wakeup Domain Range */
			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
			 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;

		cbass_mcu: bus@4000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
				 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
				 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
				 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
				 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
			bootph-all;
		};

		cbass_wakeup: bus@b00000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
				 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
				 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
			bootph-all;
		};
	};

	#include "k3-am62p-j722s-common-thermal.dtsi"
};

/* Now include peripherals for each bus segment */
#include "k3-am62p-j722s-common-main.dtsi"
#include "k3-am62p-j722s-common-mcu.dtsi"
#include "k3-am62p-j722s-common-wakeup.dtsi"

/* Include AM62P specific peripherals */
#include "k3-am62p-main.dtsi"