arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso

/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
/**
 * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
 * and ENET-2 Expansion slots of J784S4 EVM.
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>

#include "k3-serdes.h"

&{/} {
	aliases {
		ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
		ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
	};
};

&main_cpsw0 {
	pinctrl-names = "default";
	status = "okay";
};

&main_cpsw0_port1 {
	phy-mode = "usxgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
	phy-names = "mac", "serdes";
	status = "okay";
	fixed-link {
		speed = <5000>;
		full-duplex;
	};
};

&main_cpsw0_port2 {
	phy-mode = "usxgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
	phy-names = "mac", "serdes";
	status = "okay";
	fixed-link {
		speed = <5000>;
		full-duplex;
	};
};

&serdes_wiz2 {
	assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
	status = "okay";
};

&serdes2 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	serdes2_usxgmii_link: phy@2 {
		reg = <2>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USXGMII>;
		resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
	};
};

&serdes_ln_ctrl {
	idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
		      <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
		      <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
		      <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
		      <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
		      <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
};