arch/arm64/boot/dts/qcom/ipq5018.dtsi - linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
 /*
  * IPQ5018 SoC device tree source
  *
  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
  */

 #include <dt-bindings/clock/qcom,apss-ipq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>

 / {
 	interrupt-parent = <&intc>;
 	#address-cells = <2>;
 	#size-cells = <2>;

 	clocks {
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};

 		xo_board_clk: xo-board-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
 	};

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		CPU0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			operating-points-v2 = <&cpu_opp_table>;
 		};

 		CPU1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x1>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			operating-points-v2 = <&cpu_opp_table>;
 		};

 		L2_0: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
 			cache-size = <0x80000>;
 			cache-unified;
 		};
 	};

 	cpu_opp_table: opp-table-cpu {
 		compatible = "operating-points-v2";
 		opp-shared;

 		opp-800000000 {
 			opp-hz = /bits/ 64 <800000000>;
 			opp-microvolt = <1100000>;
 			clock-latency-ns = <200000>;
 		};

 		opp-1008000000 {
 			opp-hz = /bits/ 64 <1008000000>;
 			opp-microvolt = <1100000>;
 			clock-latency-ns = <200000>;
 		};
 	};

 	firmware {
 		scm {
 			compatible = "qcom,scm-ipq5018", "qcom,scm";
 			qcom,sdi-enabled;
 		};
 	};

 	memory@40000000 {
 		device_type = "memory";
 		/* We expect the bootloader to fill in the size */
 		reg = <0x0 0x40000000 0x0 0x0>;
 	};

 	pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};

 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
 	};

 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		bootloader@4a800000 {
 			reg = <0x0 0x4a800000 0x0 0x200000>;
 			no-map;
 		};

 		sbl@4aa00000 {
 			reg = <0x0 0x4aa00000 0x0 0x100000>;
 			no-map;
 		};

 		smem@4ab00000 {
 			compatible = "qcom,smem";
 			reg = <0x0 0x4ab00000 0x0 0x100000>;
 			no-map;

 			hwlocks = <&tcsr_mutex 3>;
 		};

 		tz_region: tz@4ac00000 {
 			reg = <0x0 0x4ac00000 0x0 0x200000>;
 			no-map;
 		};
 	};

 	soc: soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;

 		usbphy0: phy@5b000 {
 			compatible = "qcom,ipq5018-usb-hsphy";
 			reg = <0x0005b000 0x120>;

 			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;

 			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;

 			#phy-cells = <0>;

 			status = "disabled";
 		};

 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq5018-tlmm";
 			reg = <0x01000000 0x300000>;
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&tlmm 0 0 47>;
 			interrupt-controller;
 			#interrupt-cells = <2>;

 			uart1_pins: uart1-state {
 				pins = "gpio31", "gpio32", "gpio33", "gpio34";
 				function = "blsp1_uart1";
 				drive-strength = <8>;
 				bias-pull-down;
 			};
 		};

 		gcc: clock-controller@1800000 {
 			compatible = "qcom,gcc-ipq5018";
 			reg = <0x01800000 0x80000>;
 			clocks = <&xo_board_clk>,
 				 <&sleep_clk>,
 				 <0>,
 				 <0>,
 				 <0>,
 				 <0>,
 				 <0>,
 				 <0>,
 				 <0>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 		};

 		tcsr_mutex: hwlock@1905000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x01905000 0x20000>;
 			#hwlock-cells = <1>;
 		};

 		sdhc_1: mmc@7804000 {
 			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x7804000 0x1000>;
 			reg-names = "hc";

 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";

 			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&xo_board_clk>;
 			clock-names = "iface", "core", "xo";
 			non-removable;
 			status = "disabled";
 		};

 		blsp_dma: dma-controller@7884000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x07884000 0x1d000>;
 			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <0>;
 		};

 		blsp1_uart1: serial@78af000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x078af000 0x200>;
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 				 <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 			status = "disabled";
 		};

 		blsp1_spi1: spi@78b5000 {
 			compatible = "qcom,spi-qup-v2.2.1";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x078b5000 0x600>;
 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 				 <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};

 		usb: usb@8af8800 {
 			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
 			reg = <0x08af8800 0x400>;

 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hs_phy_irq";

 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
 				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 			clock-names = "core",
 				      "iface",
 				      "sleep",
 				      "mock_utmi";

 			resets = <&gcc GCC_USB0_BCR>;

 			qcom,select-utmi-as-pipe-clk;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;

 			status = "disabled";

 			usb_dwc: usb@8a00000 {
 				compatible = "snps,dwc3";
 				reg = <0x08a00000 0xe000>;
 				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 				clock-names = "ref";
 				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 				phy-names = "usb2-phy";
 				phys = <&usbphy0>;
 				tx-fifo-resize;
 				snps,is-utmi-l1-suspend;
 				snps,hird-threshold = /bits/ 8 <0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_u3_susphy_quirk;
 			};
 		};

 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			reg = <0x0b000000 0x1000>,  /* GICD */
 			      <0x0b002000 0x2000>,  /* GICC */
 			      <0x0b001000 0x1000>,  /* GICH */
 			      <0x0b004000 0x2000>;  /* GICV */
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 0x0b00a000 0x1ffa>;

 			v2m0: v2m@0 {
 				compatible = "arm,gic-v2m-frame";
 				reg = <0x00000000 0xff8>;
 				msi-controller;
 			};

 			v2m1: v2m@1000 {
 				compatible = "arm,gic-v2m-frame";
 				reg = <0x00001000 0xff8>;
 				msi-controller;
 			};
 		};

 		watchdog: watchdog@b017000 {
 			compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
 			reg = <0x0b017000 0x40>;
 			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 			clocks = <&sleep_clk>;
 		};

 		apcs_glb: mailbox@b111000 {
 			compatible = "qcom,ipq5018-apcs-apps-global",
 				     "qcom,ipq6018-apcs-apps-global";
 			reg = <0x0b111000 0x1000>;
 			#clock-cells = <1>;
 			clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
 			clock-names = "pll", "xo", "gpll0";
 			#mbox-cells = <1>;
 		};

 		a53pll: clock@b116000 {
 			compatible = "qcom,ipq5018-a53pll";
 			reg = <0x0b116000 0x40>;
 			#clock-cells = <0>;
 			clocks = <&xo_board_clk>;
 			clock-names = "xo";
 		};

 		timer@b120000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0b120000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;

 			frame@b120000 {
 				reg = <0x0b121000 0x1000>,
 				      <0x0b122000 0x1000>;
 				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 				frame-number = <0>;
 			};

 			frame@b123000 {
 				reg = <0xb123000 0x1000>;
 				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 				frame-number = <1>;
 				status = "disabled";
 			};

 			frame@b124000 {
 				frame-number = <2>;
 				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0x0b124000 0x1000>;
 				status = "disabled";
 			};

 			frame@b125000 {
 				reg = <0x0b125000 0x1000>;
 				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 				frame-number = <3>;
 				status = "disabled";
 			};

 			frame@b126000 {
 				reg = <0x0b126000 0x1000>;
 				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 				frame-number = <4>;
 				status = "disabled";
 			};

 			frame@b127000 {
 				reg = <0x0b127000 0x1000>;
 				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 				frame-number = <5>;
 				status = "disabled";
 			};

 			frame@b128000 {
 				reg = <0x0b128000 0x1000>;
 				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 				frame-number = <6>;
 				status = "disabled";
 			};
 		};
 	};

 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 };
	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
	/*
	* IPQ5018 SoC device tree source
	*
	* Copyright (c) 2023 The Linux Foundation. All rights reserved.
	*/

	#include <dt-bindings/clock/qcom,apss-ipq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
	#include <dt-bindings/reset/qcom,gcc-ipq5018.h>

	/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
	sleep_clk: sleep-clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	};

	xo_board_clk: xo-board-clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	};
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	enable-method = "psci";
	next-level-cache = <&L2_0>;
	clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
	operating-points-v2 = <&cpu_opp_table>;
	};

	CPU1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	enable-method = "psci";
	next-level-cache = <&L2_0>;
	clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
	operating-points-v2 = <&cpu_opp_table>;
	};

	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <2>;
	cache-size = <0x80000>;
	cache-unified;
	};
	};

	cpu_opp_table: opp-table-cpu {
	compatible = "operating-points-v2";
	opp-shared;

	opp-800000000 {
	opp-hz = /bits/ 64 <800000000>;
	opp-microvolt = <1100000>;
	clock-latency-ns = <200000>;
	};

	opp-1008000000 {
	opp-hz = /bits/ 64 <1008000000>;
	opp-microvolt = <1100000>;
	clock-latency-ns = <200000>;
	};
	};

	firmware {
	scm {
	compatible = "qcom,scm-ipq5018", "qcom,scm";
	qcom,sdi-enabled;
	};
	};

	memory@40000000 {
	device_type = "memory";
	/* We expect the bootloader to fill in the size */
	reg = <0x0 0x40000000 0x0 0x0>;
	};

	pmu {
	compatible = "arm,cortex-a53-pmu";
	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	bootloader@4a800000 {
	reg = <0x0 0x4a800000 0x0 0x200000>;
	no-map;
	};

	sbl@4aa00000 {
	reg = <0x0 0x4aa00000 0x0 0x100000>;
	no-map;
	};

	smem@4ab00000 {
	compatible = "qcom,smem";
	reg = <0x0 0x4ab00000 0x0 0x100000>;
	no-map;

	hwlocks = <&tcsr_mutex 3>;
	};

	tz_region: tz@4ac00000 {
	reg = <0x0 0x4ac00000 0x0 0x200000>;
	no-map;
	};
	};

	soc: soc@0 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;

	usbphy0: phy@5b000 {
	compatible = "qcom,ipq5018-usb-hsphy";
	reg = <0x0005b000 0x120>;

	clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;

	resets = <&gcc GCC_QUSB2_0_PHY_BCR>;

	#phy-cells = <0>;

	status = "disabled";
	};

	tlmm: pinctrl@1000000 {
	compatible = "qcom,ipq5018-tlmm";
	reg = <0x01000000 0x300000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-ranges = <&tlmm 0 0 47>;
	interrupt-controller;
	#interrupt-cells = <2>;

	uart1_pins: uart1-state {
	pins = "gpio31", "gpio32", "gpio33", "gpio34";
	function = "blsp1_uart1";
	drive-strength = <8>;
	bias-pull-down;
	};
	};

	gcc: clock-controller@1800000 {
	compatible = "qcom,gcc-ipq5018";
	reg = <0x01800000 0x80000>;
	clocks = <&xo_board_clk>,
	<&sleep_clk>,
	<0>,
	<0>,
	<0>,
	<0>,
	<0>,
	<0>,
	<0>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	#power-domain-cells = <1>;
	};

	tcsr_mutex: hwlock@1905000 {
	compatible = "qcom,tcsr-mutex";
	reg = <0x01905000 0x20000>;
	#hwlock-cells = <1>;
	};

	sdhc_1: mmc@7804000 {
	compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
	reg = <0x7804000 0x1000>;
	reg-names = "hc";

	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hc_irq", "pwr_irq";

	clocks = <&gcc GCC_SDCC1_AHB_CLK>,
	<&gcc GCC_SDCC1_APPS_CLK>,
	<&xo_board_clk>;
	clock-names = "iface", "core", "xo";
	non-removable;
	status = "disabled";
	};

	blsp_dma: dma-controller@7884000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x07884000 0x1d000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	blsp1_uart1: serial@78af000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x078af000 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp1_spi1: spi@78b5000 {
	compatible = "qcom,spi-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x078b5000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 4>, <&blsp_dma 5>;
	dma-names = "tx", "rx";
	status = "disabled";
	};

	usb: usb@8af8800 {
	compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
	reg = <0x08af8800 0x400>;

	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "hs_phy_irq";

	clocks = <&gcc GCC_USB0_MASTER_CLK>,
	<&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
	<&gcc GCC_USB0_SLEEP_CLK>,
	<&gcc GCC_USB0_MOCK_UTMI_CLK>;
	clock-names = "core",
	"iface",
	"sleep",
	"mock_utmi";

	resets = <&gcc GCC_USB0_BCR>;

	qcom,select-utmi-as-pipe-clk;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	status = "disabled";

	usb_dwc: usb@8a00000 {
	compatible = "snps,dwc3";
	reg = <0x08a00000 0xe000>;
	clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
	clock-names = "ref";
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	phy-names = "usb2-phy";
	phys = <&usbphy0>;
	tx-fifo-resize;
	snps,is-utmi-l1-suspend;
	snps,hird-threshold = /bits/ 8 <0x0>;
	snps,dis_u2_susphy_quirk;
	snps,dis_u3_susphy_quirk;
	};
	};

	intc: interrupt-controller@b000000 {
	compatible = "qcom,msm-qgic2";
	reg = <0x0b000000 0x1000>, /* GICD */
	<0x0b002000 0x2000>, /* GICC */
	<0x0b001000 0x1000>, /* GICH */
	<0x0b004000 0x2000>; /* GICV */
	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	interrupt-controller;
	#interrupt-cells = <3>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x0b00a000 0x1ffa>;

	v2m0: v2m@0 {
	compatible = "arm,gic-v2m-frame";
	reg = <0x00000000 0xff8>;
	msi-controller;
	};

	v2m1: v2m@1000 {
	compatible = "arm,gic-v2m-frame";
	reg = <0x00001000 0xff8>;
	msi-controller;
	};
	};

	watchdog: watchdog@b017000 {
	compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
	reg = <0x0b017000 0x40>;
	interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
	clocks = <&sleep_clk>;
	};

	apcs_glb: mailbox@b111000 {
	compatible = "qcom,ipq5018-apcs-apps-global",
	"qcom,ipq6018-apcs-apps-global";
	reg = <0x0b111000 0x1000>;
	#clock-cells = <1>;
	clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
	clock-names = "pll", "xo", "gpll0";
	#mbox-cells = <1>;
	};

	a53pll: clock@b116000 {
	compatible = "qcom,ipq5018-a53pll";
	reg = <0x0b116000 0x40>;
	#clock-cells = <0>;
	clocks = <&xo_board_clk>;
	clock-names = "xo";
	};

	timer@b120000 {
	compatible = "arm,armv7-timer-mem";
	reg = <0x0b120000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	frame@b120000 {
	reg = <0x0b121000 0x1000>,
	<0x0b122000 0x1000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	frame-number = <0>;
	};

	frame@b123000 {
	reg = <0xb123000 0x1000>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	frame-number = <1>;
	status = "disabled";
	};

	frame@b124000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0x0b124000 0x1000>;
	status = "disabled";
	};

	frame@b125000 {
	reg = <0x0b125000 0x1000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	frame-number = <3>;
	status = "disabled";
	};

	frame@b126000 {
	reg = <0x0b126000 0x1000>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	frame-number = <4>;
	status = "disabled";
	};

	frame@b127000 {
	reg = <0x0b127000 0x1000>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	frame-number = <5>;
	status = "disabled";
	};

	frame@b128000 {
	reg = <0x0b128000 0x1000>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	frame-number = <6>;
	status = "disabled";
	};
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};
	};