| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * SDM670 SoC device tree source, adapted from SDM845 SoC device tree |
| * |
| * Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| * Copyright (c) 2022, Richard Acayan. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/dma/qcom-gpi.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interconnect/qcom,osm-l3.h> |
| #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/phy/phy-qcom-qusb2.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { }; |
| |
| chosen { }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <610>; |
| dynamic-power-coefficient = <203>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| cache-level = <2>; |
| cache-unified; |
| L3_0: l3-cache { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <610>; |
| dynamic-power-coefficient = <203>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD1>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_100>; |
| L2_100: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <610>; |
| dynamic-power-coefficient = <203>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD2>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_200>; |
| L2_200: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <610>; |
| dynamic-power-coefficient = <203>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD3>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_300>; |
| L2_300: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <610>; |
| dynamic-power-coefficient = <203>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD4>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_400>; |
| L2_400: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <610>; |
| dynamic-power-coefficient = <203>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD5>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_500>; |
| L2_500: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <393>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu6_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD6>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_600>; |
| L2_600: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo360"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <393>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu6_opp_table>; |
| interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, |
| <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
| power-domains = <&CPU_PD7>; |
| power-domain-names = "psci"; |
| next-level-cache = <&L2_700>; |
| L2_700: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| |
| core6 { |
| cpu = <&CPU6>; |
| }; |
| |
| core7 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "little-rail-power-collapse"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <702>; |
| exit-latency-us = <915>; |
| min-residency-us = <1617>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "big-rail-power-collapse"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <526>; |
| exit-latency-us = <1854>; |
| min-residency-us = <2380>; |
| local-timer-stop; |
| }; |
| }; |
| |
| domain-idle-states { |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "domain-idle-state"; |
| arm,psci-suspend-param = <0x4100c244>; |
| entry-latency-us = <3263>; |
| exit-latency-us = <6562>; |
| min-residency-us = <9825>; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-sdm670", "qcom,scm"; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0x80000000 0x0 0x0>; |
| }; |
| |
| cpu0_opp_table: opp-table-cpu0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu0_opp1: opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-peak-kBps = <400000 4800000>; |
| }; |
| |
| cpu0_opp2: opp-576000000 { |
| opp-hz = /bits/ 64 <576000000>; |
| opp-peak-kBps = <400000 4800000>; |
| }; |
| |
| cpu0_opp3: opp-748800000 { |
| opp-hz = /bits/ 64 <748800000>; |
| opp-peak-kBps = <1200000 4800000>; |
| }; |
| |
| cpu0_opp4: opp-998400000 { |
| opp-hz = /bits/ 64 <998400000>; |
| opp-peak-kBps = <1804000 8908800>; |
| }; |
| |
| cpu0_opp5: opp-1209600000 { |
| opp-hz = /bits/ 64 <1209600000>; |
| opp-peak-kBps = <2188000 8908800>; |
| }; |
| |
| cpu0_opp6: opp-1324800000 { |
| opp-hz = /bits/ 64 <1324800000>; |
| opp-peak-kBps = <2188000 13516800>; |
| }; |
| |
| cpu0_opp7: opp-1516800000 { |
| opp-hz = /bits/ 64 <1516800000>; |
| opp-peak-kBps = <3072000 15052800>; |
| }; |
| |
| cpu0_opp8: opp-1612800000 { |
| opp-hz = /bits/ 64 <1612800000>; |
| opp-peak-kBps = <3072000 22118400>; |
| }; |
| |
| cpu0_opp9: opp-1708800000 { |
| opp-hz = /bits/ 64 <1708800000>; |
| opp-peak-kBps = <4068000 23040000>; |
| }; |
| }; |
| |
| cpu6_opp_table: opp-table-cpu6 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| cpu6_opp1: opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-peak-kBps = <400000 4800000>; |
| }; |
| |
| cpu6_opp2: opp-652800000 { |
| opp-hz = /bits/ 64 <652800000>; |
| opp-peak-kBps = <400000 4800000>; |
| }; |
| |
| cpu6_opp3: opp-825600000 { |
| opp-hz = /bits/ 64 <825600000>; |
| opp-peak-kBps = <1200000 4800000>; |
| }; |
| |
| cpu6_opp4: opp-979200000 { |
| opp-hz = /bits/ 64 <979200000>; |
| opp-peak-kBps = <1200000 4800000>; |
| }; |
| |
| cpu6_opp5: opp-1132800000 { |
| opp-hz = /bits/ 64 <1132800000>; |
| opp-peak-kBps = <2188000 8908800>; |
| }; |
| |
| cpu6_opp6: opp-1363200000 { |
| opp-hz = /bits/ 64 <1363200000>; |
| opp-peak-kBps = <4068000 12902400>; |
| }; |
| |
| cpu6_opp7: opp-1536000000 { |
| opp-hz = /bits/ 64 <1536000000>; |
| opp-peak-kBps = <4068000 12902400>; |
| }; |
| |
| cpu6_opp8: opp-1747200000 { |
| opp-hz = /bits/ 64 <1747200000>; |
| opp-peak-kBps = <4068000 15052800>; |
| }; |
| |
| cpu6_opp9: opp-1843200000 { |
| opp-hz = /bits/ 64 <1843200000>; |
| opp-peak-kBps = <4068000 15052800>; |
| }; |
| |
| cpu6_opp10: opp-1996800000 { |
| opp-hz = /bits/ 64 <1996800000>; |
| opp-peak-kBps = <6220000 19046400>; |
| }; |
| }; |
| |
| dsi_opp_table: opp-table-dsi { |
| compatible = "operating-points-v2"; |
| |
| opp-19200000 { |
| opp-hz = /bits/ 64 <19200000>; |
| required-opps = <&rpmhpd_opp_min_svs>; |
| }; |
| |
| opp-180000000 { |
| opp-hz = /bits/ 64 <180000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-275000000 { |
| opp-hz = /bits/ 64 <275000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-358000000 { |
| opp-hz = /bits/ 64 <358000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| |
| CPU_PD0: power-domain-cpu0 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD1: power-domain-cpu1 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD2: power-domain-cpu2 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD3: power-domain-cpu3 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD4: power-domain-cpu4 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD5: power-domain-cpu5 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD6: power-domain-cpu6 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD7: power-domain-cpu7 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CLUSTER_PD: power-domain-cluster { |
| #power-domain-cells = <0>; |
| domain-idle-states = <&CLUSTER_SLEEP_0>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| hyp_mem: hyp-mem@85700000 { |
| reg = <0 0x85700000 0 0x600000>; |
| no-map; |
| }; |
| |
| xbl_mem: xbl-mem@85e00000 { |
| reg = <0 0x85e00000 0 0x100000>; |
| no-map; |
| }; |
| |
| aop_mem: aop-mem@85fc0000 { |
| reg = <0 0x85fc0000 0 0x20000>; |
| no-map; |
| }; |
| |
| aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0 0x85fe0000 0 0x20000>; |
| no-map; |
| }; |
| |
| camera_mem: camera-mem@8ab00000 { |
| reg = <0 0x8ab00000 0 0x500000>; |
| no-map; |
| }; |
| |
| mpss_region: mpss@8b000000 { |
| reg = <0 0x8b000000 0 0x7e00000>; |
| no-map; |
| }; |
| |
| venus_mem: venus@92e00000 { |
| reg = <0 0x92e00000 0 0x500000>; |
| no-map; |
| }; |
| |
| wlan_msa_mem: wlan-msa@93300000 { |
| reg = <0 0x93300000 0 0x100000>; |
| no-map; |
| }; |
| |
| cdsp_mem: cdsp@93400000 { |
| reg = <0 0x93400000 0 0x800000>; |
| no-map; |
| }; |
| |
| mba_region: mba@93c00000 { |
| reg = <0 0x93c00000 0 0x200000>; |
| no-map; |
| }; |
| |
| adsp_mem: adsp@93e00000 { |
| reg = <0 0x93e00000 0 0x1e00000>; |
| no-map; |
| }; |
| |
| ipa_fw_mem: ipa-fw@95c00000 { |
| reg = <0 0x95c00000 0 0x10000>; |
| no-map; |
| }; |
| |
| ipa_gsi_mem: ipa-gsi@95c10000 { |
| reg = <0 0x95c10000 0 0x5000>; |
| no-map; |
| }; |
| |
| gpu_mem: gpu@95c15000 { |
| reg = <0 0x95c15000 0 0x2000>; |
| no-map; |
| }; |
| |
| spss_mem: spss@97b00000 { |
| reg = <0 0x97b00000 0 0x100000>; |
| no-map; |
| }; |
| |
| qseecom_mem: qseecom@9e400000 { |
| reg = <0 0x9e400000 0 0x1400000>; |
| no-map; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| soc: soc@0 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdm670"; |
| reg = <0 0x00100000 0 0x1f0000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, |
| <&sleep_clk>; |
| clock-names = "bi_tcxo", |
| "bi_tcxo_ao", |
| "sleep_clk"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| qfprom: qfprom@784000 { |
| compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; |
| reg = <0 0x00784000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| qusb2_hstx_trim: hstx-trim@1eb { |
| reg = <0x1eb 0x1>; |
| bits = <1 4>; |
| }; |
| }; |
| |
| sdhc_1: mmc@7c4000 { |
| compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0 0x007c4000 0 0x1000>, |
| <0 0x007c5000 0 0x1000>, |
| <0 0x007c8000 0 0x8000>; |
| reg-names = "hc", "cqhci", "ice"; |
| |
| interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_SDCC1_ICE_CORE_CLK>, |
| <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; |
| clock-names = "iface", "core", "xo", "ice", "bus"; |
| interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; |
| interconnect-names = "sdhc-ddr", "cpu-sdhc"; |
| operating-points-v2 = <&sdhc1_opp_table>; |
| |
| iommus = <&apps_smmu 0x140 0xf>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&sdc1_state_on>; |
| pinctrl-1 = <&sdc1_state_off>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| |
| bus-width = <8>; |
| non-removable; |
| |
| status = "disabled"; |
| |
| sdhc1_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-20000000 { |
| opp-hz = /bits/ 64 <20000000>; |
| required-opps = <&rpmhpd_opp_min_svs>; |
| opp-peak-kBps = <80000 80000>; |
| opp-avg-kBps = <52286 80000>; |
| }; |
| |
| opp-50000000 { |
| opp-hz = /bits/ 64 <50000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| opp-peak-kBps = <200000 100000>; |
| opp-avg-kBps = <130718 100000>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| opp-peak-kBps = <200000 130000>; |
| opp-avg-kBps = <130718 130000>; |
| }; |
| |
| opp-384000000 { |
| opp-hz = /bits/ 64 <384000000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| opp-peak-kBps = <4096000 4096000>; |
| opp-avg-kBps = <1338562 1338562>; |
| }; |
| }; |
| }; |
| |
| gpi_dma0: dma-controller@800000 { |
| #dma-cells = <3>; |
| compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; |
| reg = <0 0x00800000 0 0x60000>; |
| interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
| dma-channels = <13>; |
| dma-channel-mask = <0xfa>; |
| iommus = <&apps_smmu 0x16 0x0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_id_0: geniqup@8c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x008c0000 0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| iommus = <&apps_smmu 0x3 0x0>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; |
| interconnect-names = "qup-core"; |
| status = "disabled"; |
| |
| i2c0: i2c@880000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@884000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@888000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@88c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@890000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@894000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@898000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 6 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@89c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, |
| <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, |
| <&gpi_dma0 1 7 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| }; |
| |
| gpi_dma1: dma-controller@a00000 { |
| #dma-cells = <3>; |
| compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; |
| reg = <0 0x00a00000 0 0x60000>; |
| interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; |
| dma-channels = <13>; |
| dma-channel-mask = <0xfa>; |
| iommus = <&apps_smmu 0x6d6 0x0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_id_1: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x00ac0000 0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| iommus = <&apps_smmu 0x6c3 0x0>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; |
| interconnect-names = "qup-core"; |
| status = "disabled"; |
| |
| i2c8: i2c@a80000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 0 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@a84000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 1 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@a88000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 2 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@a8c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 3 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c12: i2c@a90000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 4 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c13: i2c@a94000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 5 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c14: i2c@a98000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 6 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c15: i2c@a9c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, |
| <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, |
| <&gpi_dma1 1 7 QCOM_GPI_I2C>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mem_noc: interconnect@1380000 { |
| compatible = "qcom,sdm670-mem-noc"; |
| reg = <0 0x01380000 0 0x27200>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| dc_noc: interconnect@14e0000 { |
| compatible = "qcom,sdm670-dc-noc"; |
| reg = <0 0x014e0000 0 0x400>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| config_noc: interconnect@1500000 { |
| compatible = "qcom,sdm670-config-noc"; |
| reg = <0 0x01500000 0 0x5080>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| system_noc: interconnect@1620000 { |
| compatible = "qcom,sdm670-system-noc"; |
| reg = <0 0x01620000 0 0x18080>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre1_noc: interconnect@16e0000 { |
| compatible = "qcom,sdm670-aggre1-noc"; |
| reg = <0 0x016e0000 0 0x15080>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre2_noc: interconnect@1700000 { |
| compatible = "qcom,sdm670-aggre2-noc"; |
| reg = <0 0x01700000 0 0x1f300>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mmss_noc: interconnect@1740000 { |
| compatible = "qcom,sdm670-mmss-noc"; |
| reg = <0 0x01740000 0 0x1c100>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| tlmm: pinctrl@3400000 { |
| compatible = "qcom,sdm670-tlmm"; |
| reg = <0 0x03400000 0 0xc00000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 151>; |
| wakeup-parent = <&pdc>; |
| |
| qup_i2c0_default: qup-i2c0-default-state { |
| pins = "gpio0", "gpio1"; |
| function = "qup0"; |
| }; |
| |
| qup_i2c1_default: qup-i2c1-default-state { |
| pins = "gpio17", "gpio18"; |
| function = "qup1"; |
| }; |
| |
| qup_i2c2_default: qup-i2c2-default-state { |
| pins = "gpio27", "gpio28"; |
| function = "qup2"; |
| }; |
| |
| qup_i2c3_default: qup-i2c3-default-state { |
| pins = "gpio41", "gpio42"; |
| function = "qup3"; |
| }; |
| |
| qup_i2c4_default: qup-i2c4-default-state { |
| pins = "gpio89", "gpio90"; |
| function = "qup4"; |
| }; |
| |
| qup_i2c5_default: qup-i2c5-default-state { |
| pins = "gpio85", "gpio86"; |
| function = "qup5"; |
| }; |
| |
| qup_i2c6_default: qup-i2c6-default-state { |
| pins = "gpio45", "gpio46"; |
| function = "qup6"; |
| }; |
| |
| qup_i2c7_default: qup-i2c7-default-state { |
| pins = "gpio93", "gpio94"; |
| function = "qup7"; |
| }; |
| |
| qup_i2c8_default: qup-i2c8-default-state { |
| pins = "gpio65", "gpio66"; |
| function = "qup8"; |
| }; |
| |
| qup_i2c9_default: qup-i2c9-default-state { |
| pins = "gpio6", "gpio7"; |
| function = "qup9"; |
| }; |
| |
| qup_i2c10_default: qup-i2c10-default-state { |
| pins = "gpio55", "gpio56"; |
| function = "qup10"; |
| }; |
| |
| qup_i2c11_default: qup-i2c11-default-state { |
| pins = "gpio31", "gpio32"; |
| function = "qup11"; |
| }; |
| |
| qup_i2c12_default: qup-i2c12-default-state { |
| pins = "gpio49", "gpio50"; |
| function = "qup12"; |
| }; |
| |
| qup_i2c13_default: qup-i2c13-default-state { |
| pins = "gpio105", "gpio106"; |
| function = "qup13"; |
| }; |
| |
| qup_i2c14_default: qup-i2c14-default-state { |
| pins = "gpio33", "gpio34"; |
| function = "qup14"; |
| }; |
| |
| qup_i2c15_default: qup-i2c15-default-state { |
| pins = "gpio81", "gpio82"; |
| function = "qup15"; |
| }; |
| |
| sdc1_state_on: sdc1-on-state { |
| clk-pins { |
| pins = "sdc1_clk"; |
| bias-disable; |
| drive-strength = <16>; |
| }; |
| |
| cmd-pins { |
| pins = "sdc1_cmd"; |
| bias-pull-up; |
| drive-strength = <10>; |
| }; |
| |
| data-pins { |
| pins = "sdc1_data"; |
| bias-pull-up; |
| drive-strength = <10>; |
| }; |
| |
| rclk-pins { |
| pins = "sdc1_rclk"; |
| bias-pull-down; |
| }; |
| }; |
| |
| sdc1_state_off: sdc1-off-state { |
| clk-pins { |
| pins = "sdc1_clk"; |
| bias-disable; |
| drive-strength = <2>; |
| }; |
| |
| cmd-pins { |
| pins = "sdc1_cmd"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| |
| data-pins { |
| pins = "sdc1_data"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| |
| rclk-pins { |
| pins = "sdc1_rclk"; |
| bias-pull-down; |
| }; |
| }; |
| }; |
| |
| usb_1_hsphy: phy@88e2000 { |
| compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; |
| reg = <0 0x088e2000 0 0x400>; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
| |
| nvmem-cells = <&qusb2_hstx_trim>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_1: usb@a6f8800 { |
| compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; |
| reg = <0 0x0a6f8800 0 0x400>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-ranges; |
| |
| clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
| <&gcc GCC_USB30_PRIM_MASTER_CLK>, |
| <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
| <&gcc GCC_USB30_PRIM_SLEEP_CLK>, |
| <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; |
| clock-names = "cfg_noc", |
| "core", |
| "iface", |
| "sleep", |
| "mock_utmi"; |
| |
| assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_PRIM_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <150000000>; |
| |
| interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, |
| <&pdc 8 IRQ_TYPE_EDGE_BOTH>, |
| <&pdc 9 IRQ_TYPE_EDGE_BOTH>; |
| interrupt-names = "hs_phy_irq", "ss_phy_irq", |
| "dm_hs_phy_irq", "dp_hs_phy_irq"; |
| |
| power-domains = <&gcc USB30_PRIM_GDSC>; |
| |
| resets = <&gcc GCC_USB30_PRIM_BCR>; |
| |
| interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, |
| <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; |
| interconnect-names = "usb-ddr", "apps-usb"; |
| |
| status = "disabled"; |
| |
| usb_1_dwc3: usb@a600000 { |
| compatible = "snps,dwc3"; |
| reg = <0 0x0a600000 0 0xcd00>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x740 0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_enblslpm_quirk; |
| phys = <&usb_1_hsphy>; |
| phy-names = "usb2-phy"; |
| }; |
| }; |
| |
| pdc: interrupt-controller@b220000 { |
| compatible = "qcom,sdm670-pdc", "qcom,pdc"; |
| reg = <0 0x0b220000 0 0x30000>; |
| qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, |
| <54 534 24>, <79 559 15>, <94 609 15>, |
| <115 630 7>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| spmi_bus: spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0 0x0c440000 0 0x1100>, |
| <0 0x0c600000 0 0x2000000>, |
| <0 0x0e600000 0 0x100000>, |
| <0 0x0e700000 0 0xa0000>, |
| <0 0x0c40a000 0 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| mdss: display-subsystem@ae00000 { |
| compatible = "qcom,sdm670-mdss"; |
| reg = <0 0x0ae00000 0 0x1000>; |
| reg-names = "mdss"; |
| |
| power-domains = <&dispcc MDSS_GDSC>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>; |
| clock-names = "iface", "core"; |
| |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, |
| <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; |
| interconnect-names = "mdp0-mem", "mdp1-mem"; |
| |
| iommus = <&apps_smmu 0x880 0x8>, |
| <&apps_smmu 0xc80 0x8>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| mdss_mdp: display-controller@ae01000 { |
| compatible = "qcom,sdm670-dpu"; |
| reg = <0 0x0ae01000 0 0x8f000>, |
| <0 0x0aeb0000 0 0x2008>; |
| reg-names = "mdp", "vbif"; |
| |
| clocks = <&gcc GCC_DISP_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>, |
| <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; |
| |
| assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| assigned-clock-rates = <19200000>; |
| operating-points-v2 = <&mdp_opp_table>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dpu_intf0_out: endpoint { |
| remote-endpoint = <&mdss_dsi0_in>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dpu_intf1_out: endpoint { |
| remote-endpoint = <&mdss_dsi1_in>; |
| }; |
| }; |
| }; |
| |
| mdp_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-19200000 { |
| opp-hz = /bits/ 64 <19200000>; |
| required-opps = <&rpmhpd_opp_min_svs>; |
| }; |
| |
| opp-171428571 { |
| opp-hz = /bits/ 64 <171428571>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-358000000 { |
| opp-hz = /bits/ 64 <358000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| |
| opp-430000000 { |
| opp-hz = /bits/ 64 <430000000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| }; |
| }; |
| }; |
| |
| mdss_dsi0: dsi@ae94000 { |
| compatible = "qcom,sdm670-dsi-ctrl", |
| "qcom,mdss-dsi-ctrl"; |
| reg = <0 0x0ae94000 0 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <4>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, |
| <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, |
| <&dispcc DISP_CC_MDSS_PCLK0_CLK>, |
| <&dispcc DISP_CC_MDSS_ESC0_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AXI_CLK>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus"; |
| assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, |
| <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; |
| assigned-clock-parents = <&mdss_dsi0_phy 0>, |
| <&mdss_dsi0_phy 1>; |
| |
| operating-points-v2 = <&dsi_opp_table>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| |
| phys = <&mdss_dsi0_phy>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| mdss_dsi0_in: endpoint { |
| remote-endpoint = <&dpu_intf0_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| mdss_dsi0_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi0_phy: phy@ae94400 { |
| compatible = "qcom,dsi-phy-10nm"; |
| reg = <0 0x0ae94400 0 0x200>, |
| <0 0x0ae94600 0 0x280>, |
| <0 0x0ae94a00 0 0x1e0>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", "ref"; |
| |
| status = "disabled"; |
| }; |
| |
| mdss_dsi1: dsi@ae96000 { |
| compatible = "qcom,sdm670-dsi-ctrl", |
| "qcom,mdss-dsi-ctrl"; |
| reg = <0 0x0ae96000 0 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <5>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, |
| <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, |
| <&dispcc DISP_CC_MDSS_PCLK1_CLK>, |
| <&dispcc DISP_CC_MDSS_ESC1_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AXI_CLK>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus"; |
| assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, |
| <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; |
| assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; |
| |
| operating-points-v2 = <&dsi_opp_table>; |
| power-domains = <&rpmhpd SDM670_CX>; |
| |
| phys = <&mdss_dsi1_phy>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| mdss_dsi1_in: endpoint { |
| remote-endpoint = <&dpu_intf1_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| mdss_dsi1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi1_phy: phy@ae96400 { |
| compatible = "qcom,dsi-phy-10nm"; |
| reg = <0 0x0ae96400 0 0x200>, |
| <0 0x0ae96600 0 0x280>, |
| <0 0x0ae96a00 0 0x10e>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", "ref"; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| dispcc: clock-controller@af00000 { |
| compatible = "qcom,sdm845-dispcc"; |
| reg = <0 0x0af00000 0 0x10000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_DISP_GPLL0_CLK_SRC>, |
| <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, |
| <&mdss_dsi0_phy 0>, |
| <&mdss_dsi0_phy 1>, |
| <&mdss_dsi1_phy 0>, |
| <&mdss_dsi1_phy 1>, |
| <0>, |
| <0>; |
| clock-names = "bi_tcxo", |
| "gcc_disp_gpll0_clk_src", |
| "gcc_disp_gpll0_div_clk_src", |
| "dsi0_phy_pll_out_byteclk", |
| "dsi0_phy_pll_out_dsiclk", |
| "dsi1_phy_pll_out_byteclk", |
| "dsi1_phy_pll_out_dsiclk", |
| "dp_link_clk_divsel_ten", |
| "dp_vco_divided_clk_src_mux"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| apps_smmu: iommu@15000000 { |
| compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; |
| reg = <0 0x15000000 0 0x80000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <1>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gladiator_noc: interconnect@17900000 { |
| compatible = "qcom,sdm670-gladiator-noc"; |
| reg = <0 0x17900000 0 0xd080>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| apps_rsc: rsc@179c0000 { |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0 0x179c0000 0 0x10000>, |
| <0 0x179d0000 0 0x10000>, |
| <0 0x179e0000 0 0x10000>; |
| reg-names = "drv-0", "drv-1", "drv-2"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| label = "apps_rsc"; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, |
| <CONTROL_TCS 1>; |
| power-domains = <&CLUSTER_PD>; |
| |
| apps_bcm_voter: bcm-voter { |
| compatible = "qcom,bcm-voter"; |
| }; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sdm670-rpmh-clk"; |
| #clock-cells = <1>; |
| clock-names = "xo"; |
| clocks = <&xo_board>; |
| }; |
| |
| rpmhpd: power-controller { |
| compatible = "qcom,sdm670-rpmhpd"; |
| #power-domain-cells = <1>; |
| operating-points-v2 = <&rpmhpd_opp_table>; |
| |
| rpmhpd_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| rpmhpd_opp_ret: opp1 { |
| opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| }; |
| |
| rpmhpd_opp_min_svs: opp2 { |
| opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
| }; |
| |
| rpmhpd_opp_low_svs: opp3 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| }; |
| |
| rpmhpd_opp_svs: opp4 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| |
| rpmhpd_opp_svs_l1: opp5 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| |
| rpmhpd_opp_nom: opp6 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| rpmhpd_opp_nom_l1: opp7 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| rpmhpd_opp_nom_l2: opp8 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
| }; |
| |
| rpmhpd_opp_turbo: opp9 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| }; |
| |
| rpmhpd_opp_turbo_l1: opp10 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| }; |
| }; |
| }; |
| }; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0 0x17a00000 0 0x10000>, /* GICD */ |
| <0 0x17a60000 0 0x100000>; /* GICR * 8 */ |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <3>; |
| }; |
| |
| osm_l3: interconnect@17d41000 { |
| compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; |
| reg = <0 0x17d41000 0 0x1400>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
| clock-names = "xo", "alternate"; |
| |
| #interconnect-cells = <1>; |
| }; |
| |
| cpufreq_hw: cpufreq@17d43000 { |
| compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw"; |
| reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; |
| reg-names = "freq-domain0", "freq-domain1"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
| clock-names = "xo", "alternate"; |
| |
| #freq-domain-cells = <1>; |
| }; |
| }; |
| }; |
