| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NVIDIA Tegra USB PHY |
| |
| maintainers: |
| - Dmitry Osipenko <digetx@gmail.com> |
| - Jon Hunter <jonathanh@nvidia.com> |
| - Thierry Reding <thierry.reding@gmail.com> |
| |
| properties: |
| compatible: |
| oneOf: |
| - items: |
| - enum: |
| - nvidia,tegra124-usb-phy |
| - nvidia,tegra114-usb-phy |
| - enum: |
| - nvidia,tegra30-usb-phy |
| - items: |
| - enum: |
| - nvidia,tegra30-usb-phy |
| - nvidia,tegra20-usb-phy |
| |
| reg: |
| minItems: 1 |
| maxItems: 2 |
| description: | |
| PHY0 and PHY2 share power and ground, PHY0 contains shared registers. |
| PHY0 and PHY2 must specify two register sets, where the first set is |
| PHY own registers and the second set is the PHY0 registers. |
| |
| clocks: |
| anyOf: |
| - items: |
| - description: Registers clock |
| - description: Main PHY clock |
| |
| - items: |
| - description: Registers clock |
| - description: Main PHY clock |
| - description: ULPI PHY clock |
| |
| - items: |
| - description: Registers clock |
| - description: Main PHY clock |
| - description: UTMI pads control registers clock |
| |
| - items: |
| - description: Registers clock |
| - description: Main PHY clock |
| - description: UTMI timeout clock |
| - description: UTMI pads control registers clock |
| |
| clock-names: |
| oneOf: |
| - items: |
| - const: reg |
| - const: pll_u |
| |
| - items: |
| - const: reg |
| - const: pll_u |
| - const: ulpi-link |
| |
| - items: |
| - const: reg |
| - const: pll_u |
| - const: utmi-pads |
| |
| - items: |
| - const: reg |
| - const: pll_u |
| - const: timer |
| - const: utmi-pads |
| |
| interrupts: |
| maxItems: 1 |
| |
| resets: |
| oneOf: |
| - maxItems: 1 |
| description: PHY reset |
| |
| - items: |
| - description: PHY reset |
| - description: UTMI pads reset |
| |
| reset-names: |
| oneOf: |
| - const: usb |
| |
| - items: |
| - const: usb |
| - const: utmi-pads |
| |
| "#phy-cells": |
| const: 0 |
| |
| phy_type: |
| $ref: /schemas/types.yaml#/definitions/string |
| enum: [utmi, ulpi, hsic] |
| |
| dr_mode: |
| $ref: /schemas/types.yaml#/definitions/string |
| enum: [host, peripheral, otg] |
| default: host |
| |
| vbus-supply: |
| description: Regulator controlling USB VBUS. |
| |
| nvidia,has-legacy-mode: |
| description: | |
| Indicates whether this controller can operate in legacy mode |
| (as APX 2500 / 2600). In legacy mode some registers are accessed |
| through the APB_MISC base address instead of the USB controller. |
| type: boolean |
| |
| nvidia,is-wired: |
| description: | |
| Indicates whether we can do certain kind of power optimizations for |
| the devices that are always connected. e.g. modem. |
| type: boolean |
| |
| nvidia,has-utmi-pad-registers: |
| description: | |
| Indicates whether this controller contains the UTMI pad control |
| registers common to all USB controllers. |
| type: boolean |
| |
| nvidia,hssync-start-delay: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 31 |
| description: | |
| Number of 480 MHz clock cycles to wait before start of sync launches |
| RxActive. |
| |
| nvidia,elastic-limit: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 31 |
| description: Variable FIFO Depth of elastic input store. |
| |
| nvidia,idle-wait-delay: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 31 |
| description: | |
| Number of 480 MHz clock cycles of idle to wait before declare IDLE. |
| |
| nvidia,term-range-adj: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 15 |
| description: Range adjustment on terminations. |
| |
| nvidia,xcvr-setup: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 127 |
| description: Input of XCVR cell, HS driver output control. |
| |
| nvidia,xcvr-setup-use-fuses: |
| description: Indicates that the value is read from the on-chip fuses. |
| type: boolean |
| |
| nvidia,xcvr-lsfslew: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 3 |
| description: LS falling slew rate control. |
| |
| nvidia,xcvr-lsrslew: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 3 |
| description: LS rising slew rate control. |
| |
| nvidia,xcvr-hsslew: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 511 |
| description: HS slew rate control. |
| |
| nvidia,hssquelch-level: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 3 |
| description: HS squelch detector level. |
| |
| nvidia,hsdiscon-level: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| minimum: 0 |
| maximum: 7 |
| description: HS disconnect detector level. |
| |
| nvidia,phy-reset-gpio: |
| maxItems: 1 |
| description: GPIO used to reset the PHY. |
| |
| nvidia,pmc: |
| $ref: /schemas/types.yaml#/definitions/phandle-array |
| items: |
| - items: |
| - description: Phandle to Power Management controller. |
| - description: USB controller ID. |
| description: |
| Phandle to Power Management controller. |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - resets |
| - reset-names |
| - "#phy-cells" |
| - phy_type |
| |
| additionalProperties: false |
| |
| allOf: |
| - if: |
| properties: |
| phy_type: |
| const: utmi |
| |
| then: |
| properties: |
| reg: |
| minItems: 2 |
| maxItems: 2 |
| |
| resets: |
| maxItems: 2 |
| |
| reset-names: |
| maxItems: 2 |
| |
| required: |
| - nvidia,hssync-start-delay |
| - nvidia,elastic-limit |
| - nvidia,idle-wait-delay |
| - nvidia,term-range-adj |
| - nvidia,xcvr-lsfslew |
| - nvidia,xcvr-lsrslew |
| |
| anyOf: |
| - required: ["nvidia,xcvr-setup"] |
| - required: ["nvidia,xcvr-setup-use-fuses"] |
| |
| if: |
| properties: |
| compatible: |
| contains: |
| const: nvidia,tegra30-usb-phy |
| |
| then: |
| properties: |
| clocks: |
| maxItems: 3 |
| |
| clock-names: |
| items: |
| - const: reg |
| - const: pll_u |
| - const: utmi-pads |
| |
| required: |
| - nvidia,xcvr-hsslew |
| - nvidia,hssquelch-level |
| - nvidia,hsdiscon-level |
| |
| else: |
| properties: |
| clocks: |
| maxItems: 4 |
| |
| clock-names: |
| items: |
| - const: reg |
| - const: pll_u |
| - const: timer |
| - const: utmi-pads |
| |
| - if: |
| properties: |
| phy_type: |
| const: ulpi |
| |
| then: |
| properties: |
| reg: |
| minItems: 1 |
| maxItems: 1 |
| |
| clocks: |
| minItems: 2 |
| maxItems: 3 |
| |
| clock-names: |
| minItems: 2 |
| maxItems: 3 |
| |
| oneOf: |
| - items: |
| - const: reg |
| - const: pll_u |
| |
| - items: |
| - const: reg |
| - const: pll_u |
| - const: ulpi-link |
| |
| resets: |
| minItems: 1 |
| maxItems: 2 |
| |
| reset-names: |
| minItems: 1 |
| maxItems: 2 |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/tegra124-car.h> |
| |
| usb-phy@7d008000 { |
| compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| reg = <0x7d008000 0x4000>, |
| <0x7d000000 0x4000>; |
| interrupts = <0 97 4>; |
| phy_type = "utmi"; |
| clocks = <&tegra_car TEGRA124_CLK_USB3>, |
| <&tegra_car TEGRA124_CLK_PLL_U>, |
| <&tegra_car TEGRA124_CLK_USBD>; |
| clock-names = "reg", "pll_u", "utmi-pads"; |
| resets = <&tegra_car 59>, <&tegra_car 22>; |
| reset-names = "usb", "utmi-pads"; |
| #phy-cells = <0>; |
| nvidia,hssync-start-delay = <0>; |
| nvidia,idle-wait-delay = <17>; |
| nvidia,elastic-limit = <16>; |
| nvidia,term-range-adj = <6>; |
| nvidia,xcvr-setup = <9>; |
| nvidia,xcvr-lsfslew = <0>; |
| nvidia,xcvr-lsrslew = <3>; |
| nvidia,hssquelch-level = <2>; |
| nvidia,hsdiscon-level = <5>; |
| nvidia,xcvr-hsslew = <12>; |
| nvidia,pmc = <&tegra_pmc 2>; |
| }; |
| |
| - | |
| #include <dt-bindings/clock/tegra20-car.h> |
| |
| usb-phy@c5004000 { |
| compatible = "nvidia,tegra20-usb-phy"; |
| reg = <0xc5004000 0x4000>; |
| interrupts = <0 21 4>; |
| phy_type = "ulpi"; |
| clocks = <&tegra_car TEGRA20_CLK_USB2>, |
| <&tegra_car TEGRA20_CLK_PLL_U>, |
| <&tegra_car TEGRA20_CLK_CDEV2>; |
| clock-names = "reg", "pll_u", "ulpi-link"; |
| resets = <&tegra_car 58>, <&tegra_car 22>; |
| reset-names = "usb", "utmi-pads"; |
| #phy-cells = <0>; |
| nvidia,pmc = <&tegra_pmc 1>; |
| }; |
