| NVIDIA Tegra20 MC(Memory Controller) |
| |
| Required properties: |
| - compatible : "nvidia,tegra20-mc-gart" |
| - reg : Should contain 2 register ranges: physical base address and length of |
| the controller's registers and the GART aperture respectively. |
| - clocks: Must contain an entry for each entry in clock-names. |
| See ../clocks/clock-bindings.txt for details. |
| - clock-names: Must include the following entries: |
| - mc: the module's clock input |
| - interrupts : Should contain MC General interrupt. |
| - #reset-cells : Should be 1. This cell represents memory client module ID. |
| The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h> |
| or in the TRM documentation. |
| - #iommu-cells: Should be 0. This cell represents the number of cells in an |
| IOMMU specifier needed to encode an address. GART supports only a single |
| address space that is shared by all devices, therefore no additional |
| information needed for the address encoding. |
| - #interconnect-cells : Should be 1. This cell represents memory client. |
| The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>. |
| |
| Example: |
| mc: memory-controller@7000f000 { |
| compatible = "nvidia,tegra20-mc-gart"; |
| reg = <0x7000f000 0x400 /* controller registers */ |
| 0x58000000 0x02000000>; /* GART aperture */ |
| clocks = <&tegra_car TEGRA20_CLK_MC>; |
| clock-names = "mc"; |
| interrupts = <GIC_SPI 77 0x04>; |
| #reset-cells = <1>; |
| #iommu-cells = <0>; |
| #interconnect-cells = <1>; |
| }; |
| |
| video-codec@6001a000 { |
| compatible = "nvidia,tegra20-vde"; |
| ... |
| resets = <&mc TEGRA20_MC_RESET_VDE>; |
| iommus = <&mc>; |
| }; |