| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ |
| #define ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ |
| |
| /* |
| ***************************************** |
| * SRAM_Y0_X3_RTR (Prototype: IC_RTR) |
| ***************************************** |
| */ |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_E_ARB 0x20D100 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_W_ARB 0x20D104 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB 0x20D110 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_E_ARB_MAX 0x20D120 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_W_ARB_MAX 0x20D124 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_L_ARB_MAX 0x20D130 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB 0x20D140 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB 0x20D144 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB 0x20D148 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB 0x20D160 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB 0x20D164 |
| |
| #define mmSRAM_Y0_X3_RTR_HBW_WR_RS_L_ARB 0x20D168 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_E_ARB 0x20D200 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_W_ARB 0x20D204 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_RD_RQ_L_ARB 0x20D210 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_E_ARB_MAX 0x20D220 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_W_ARB_MAX 0x20D224 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_L_ARB_MAX 0x20D230 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_DATA_E_ARB 0x20D240 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_DATA_W_ARB 0x20D244 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_DATA_L_ARB 0x20D248 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_WR_RS_E_ARB 0x20D260 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_WR_RS_W_ARB 0x20D264 |
| |
| #define mmSRAM_Y0_X3_RTR_LBW_WR_RS_L_ARB 0x20D268 |
| |
| #define mmSRAM_Y0_X3_RTR_DBG_E_ARB 0x20D300 |
| |
| #define mmSRAM_Y0_X3_RTR_DBG_W_ARB 0x20D304 |
| |
| #define mmSRAM_Y0_X3_RTR_DBG_L_ARB 0x20D310 |
| |
| #define mmSRAM_Y0_X3_RTR_DBG_E_ARB_MAX 0x20D320 |
| |
| #define mmSRAM_Y0_X3_RTR_DBG_W_ARB_MAX 0x20D324 |
| |
| #define mmSRAM_Y0_X3_RTR_DBG_L_ARB_MAX 0x20D330 |
| |
| #endif /* ASIC_REG_SRAM_Y0_X3_RTR_REGS_H_ */ |