| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC0_EML_CFG_REGS_H_ |
| #define ASIC_REG_TPC0_EML_CFG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC0_EML_CFG (Prototype: TPC_EML_CFG) |
| ***************************************** |
| */ |
| |
| #define mmTPC0_EML_CFG_DBG_CNT 0x3040000 |
| |
| #define mmTPC0_EML_CFG_DBG_STS 0x3040004 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_0 0x3040008 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_1 0x304000C |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_2 0x3040010 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_3 0x3040014 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_4 0x3040018 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_5 0x304001C |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_6 0x3040020 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_7 0x3040024 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_0 0x3040028 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_1 0x304002C |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_2 0x3040030 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_3 0x3040034 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_4 0x3040038 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_5 0x304003C |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_6 0x3040040 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_7 0x3040044 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_0 0x3040048 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_1 0x304004C |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_2 0x3040050 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_3 0x3040054 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_4 0x3040058 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_5 0x304005C |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_6 0x3040060 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_COUNT_MATCH_7 0x3040064 |
| |
| #define mmTPC0_EML_CFG_DBG_PADD_EN 0x3040068 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_HIGH_0 0x304006C |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_HIGH_1 0x3040070 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_LOW_0 0x3040074 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_LOW_1 0x3040078 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_0 0x304007C |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_1 0x3040080 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_0 0x3040084 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_1 0x3040088 |
| |
| #define mmTPC0_EML_CFG_DBG_VPADD_EN 0x304008C |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_HIGH_0 0x3040090 |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_HIGH_1 0x3040094 |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_LOW_0 0x3040098 |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_LOW_1 0x304009C |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_0 0x30400A0 |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_1 0x30400A4 |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_0 0x30400A8 |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_1 0x30400AC |
| |
| #define mmTPC0_EML_CFG_DBG_SPADD_EN 0x30400B0 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_0 0x30400B4 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_1 0x30400B8 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_0 0x30400BC |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_MSB_LOW_1 0x30400C0 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_0 0x30400C4 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_1 0x30400C8 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_0 0x30400CC |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_LSB_LOW_1 0x30400D0 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_0 0x30400D4 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_1 0x30400D8 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_0 0x30400DC |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_1 0x30400E0 |
| |
| #define mmTPC0_EML_CFG_DBG_AGUADD_EN 0x30400E4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_0 0x30400E8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_1 0x30400EC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_0 0x30400F0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_1 0x30400F4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_0 0x30400F8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_1 0x30400FC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_0 0x3040100 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_1 0x3040104 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_0 0x3040108 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_1 0x304010C |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_0 0x3040110 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_1 0x3040114 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWADD_EN 0x3040118 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_0 0x304011C |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_1 0x3040120 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_0 0x3040124 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_1 0x3040128 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_0 0x304012C |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_1 0x3040130 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_0 0x3040134 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_1 0x3040138 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_0 0x304013C |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_1 0x3040140 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_0 0x3040144 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_1 0x3040148 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWADD_EN 0x304014C |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_0 0x3040150 |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_1 0x3040154 |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_0 0x3040158 |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_1 0x304015C |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_0 0x3040160 |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_1 0x3040164 |
| |
| #define mmTPC0_EML_CFG_DBG_SPDATA_EN 0x3040168 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_0 0x304016C |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_1 0x3040170 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_2 0x3040174 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_3 0x3040178 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_4 0x304017C |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_5 0x3040180 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_6 0x3040184 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_7 0x3040188 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_8 0x304018C |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_9 0x3040190 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_10 0x3040194 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_11 0x3040198 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_12 0x304019C |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_13 0x30401A0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_14 0x30401A4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_15 0x30401A8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_16 0x30401AC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_17 0x30401B0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_18 0x30401B4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_19 0x30401B8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_20 0x30401BC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_21 0x30401C0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_22 0x30401C4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_23 0x30401C8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_24 0x30401CC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_25 0x30401D0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_26 0x30401D4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_27 0x30401D8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_28 0x30401DC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_29 0x30401E0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_30 0x30401E4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_31 0x30401E8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_COUNT 0x30401EC |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH 0x30401F0 |
| |
| #define mmTPC0_EML_CFG_DBG_AXIHBWDATA_EN 0x30401F4 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWDATA 0x30401F8 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWDATA_COUNT 0x30401FC |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH 0x3040200 |
| |
| #define mmTPC0_EML_CFG_DBG_AXILBWDATA_EN 0x3040204 |
| |
| #define mmTPC0_EML_CFG_DBG_D0_PC 0x3040208 |
| |
| #define mmTPC0_EML_CFG_RTTCONFIG 0x3040300 |
| |
| #define mmTPC0_EML_CFG_RTTPREDICATE 0x3040304 |
| |
| #define mmTPC0_EML_CFG_RTTPREDICATE_INTV 0x3040308 |
| |
| #define mmTPC0_EML_CFG_RTTTS 0x304030C |
| |
| #define mmTPC0_EML_CFG_RTTTS_INTV 0x3040310 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_0 0x3040314 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_1 0x3040318 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_2 0x304031C |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_3 0x3040320 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_4 0x3040324 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_5 0x3040328 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_6 0x304032C |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_7 0x3040330 |
| |
| #define mmTPC0_EML_CFG_DBG_INST_INSERT_CTL 0x3040334 |
| |
| #endif /* ASIC_REG_TPC0_EML_CFG_REGS_H_ */ |