| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC_PLL_REGS_H_ |
| #define ASIC_REG_TPC_PLL_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC_PLL (Prototype: PLL) |
| ***************************************** |
| */ |
| |
| #define mmTPC_PLL_NR 0xE01100 |
| |
| #define mmTPC_PLL_NF 0xE01104 |
| |
| #define mmTPC_PLL_OD 0xE01108 |
| |
| #define mmTPC_PLL_NB 0xE0110C |
| |
| #define mmTPC_PLL_CFG 0xE01110 |
| |
| #define mmTPC_PLL_LOSE_MASK 0xE01120 |
| |
| #define mmTPC_PLL_LOCK_INTR 0xE01128 |
| |
| #define mmTPC_PLL_LOCK_BYPASS 0xE0112C |
| |
| #define mmTPC_PLL_DATA_CHNG 0xE01130 |
| |
| #define mmTPC_PLL_RST 0xE01134 |
| |
| #define mmTPC_PLL_SLIP_WD_CNTR 0xE01150 |
| |
| #define mmTPC_PLL_DIV_FACTOR_0 0xE01200 |
| |
| #define mmTPC_PLL_DIV_FACTOR_1 0xE01204 |
| |
| #define mmTPC_PLL_DIV_FACTOR_2 0xE01208 |
| |
| #define mmTPC_PLL_DIV_FACTOR_3 0xE0120C |
| |
| #define mmTPC_PLL_DIV_FACTOR_CMD_0 0xE01220 |
| |
| #define mmTPC_PLL_DIV_FACTOR_CMD_1 0xE01224 |
| |
| #define mmTPC_PLL_DIV_FACTOR_CMD_2 0xE01228 |
| |
| #define mmTPC_PLL_DIV_FACTOR_CMD_3 0xE0122C |
| |
| #define mmTPC_PLL_DIV_SEL_0 0xE01280 |
| |
| #define mmTPC_PLL_DIV_SEL_1 0xE01284 |
| |
| #define mmTPC_PLL_DIV_SEL_2 0xE01288 |
| |
| #define mmTPC_PLL_DIV_SEL_3 0xE0128C |
| |
| #define mmTPC_PLL_DIV_EN_0 0xE012A0 |
| |
| #define mmTPC_PLL_DIV_EN_1 0xE012A4 |
| |
| #define mmTPC_PLL_DIV_EN_2 0xE012A8 |
| |
| #define mmTPC_PLL_DIV_EN_3 0xE012AC |
| |
| #define mmTPC_PLL_DIV_FACTOR_BUSY_0 0xE012C0 |
| |
| #define mmTPC_PLL_DIV_FACTOR_BUSY_1 0xE012C4 |
| |
| #define mmTPC_PLL_DIV_FACTOR_BUSY_2 0xE012C8 |
| |
| #define mmTPC_PLL_DIV_FACTOR_BUSY_3 0xE012CC |
| |
| #define mmTPC_PLL_CLK_GATER 0xE01300 |
| |
| #define mmTPC_PLL_CLK_RLX_0 0xE01310 |
| |
| #define mmTPC_PLL_CLK_RLX_1 0xE01314 |
| |
| #define mmTPC_PLL_CLK_RLX_2 0xE01318 |
| |
| #define mmTPC_PLL_CLK_RLX_3 0xE0131C |
| |
| #define mmTPC_PLL_REF_CNTR_PERIOD 0xE01400 |
| |
| #define mmTPC_PLL_REF_LOW_THRESHOLD 0xE01410 |
| |
| #define mmTPC_PLL_REF_HIGH_THRESHOLD 0xE01420 |
| |
| #define mmTPC_PLL_PLL_NOT_STABLE 0xE01430 |
| |
| #define mmTPC_PLL_FREQ_CALC_EN 0xE01440 |
| |
| #endif /* ASIC_REG_TPC_PLL_REGS_H_ */ |