| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Qualcomm Display Clock & Reset Controller for SM7150 |
| |
| maintainers: |
| - Danila Tikhonov <danila@jiaxyga.com> |
| - David Wronek <david@mainlining.org> |
| - Jens Reidel <adrian@travitia.xyz> |
| |
| description: | |
| Qualcomm display clock control module provides the clocks, resets and power |
| domains on SM7150. |
| |
| See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h |
| |
| properties: |
| compatible: |
| const: qcom,sm7150-dispcc |
| |
| clocks: |
| items: |
| - description: Board XO source |
| - description: Board Always On XO source |
| - description: GPLL0 source from GCC |
| - description: Sleep clock source |
| - description: Byte clock from MDSS DSI PHY0 |
| - description: Pixel clock from MDSS DSI PHY0 |
| - description: Byte clock from MDSS DSI PHY1 |
| - description: Pixel clock from MDSS DSI PHY1 |
| - description: Link clock from DP PHY |
| - description: VCO DIV clock from DP PHY |
| |
| power-domains: |
| maxItems: 1 |
| description: |
| CX power domain. |
| |
| required: |
| - compatible |
| - clocks |
| - power-domains |
| |
| allOf: |
| - $ref: qcom,gcc.yaml# |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/qcom,sm7150-gcc.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/power/qcom,rpmhpd.h> |
| clock-controller@af00000 { |
| compatible = "qcom,sm7150-dispcc"; |
| reg = <0x0af00000 0x200000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, |
| <&gcc GCC_DISP_GPLL0_CLK_SRC>, |
| <&sleep_clk>, |
| <&mdss_dsi0_phy 0>, |
| <&mdss_dsi0_phy 1>, |
| <&mdss_dsi1_phy 0>, |
| <&mdss_dsi1_phy 1>, |
| <&dp_phy 0>, |
| <&dp_phy 1>; |
| power-domains = <&rpmhpd RPMHPD_CX>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| ... |