arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019
 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
 */

#include "../../armv7-m.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/imxrt1050-clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	clocks {
		osc: osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};

		osc3M: osc3M {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <3000000>;
		};
	};

	soc {
		lpuart1: serial@40184000 {
			compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
			reg = <0x40184000 0x4000>;
			interrupts = <20>;
			clocks = <&clks IMXRT1050_CLK_LPUART1>;
			clock-names = "ipg";
			status = "disabled";
		};

		iomuxc: pinctrl@401f8000 {
			compatible = "fsl,imxrt1050-iomuxc";
			reg = <0x401f8000 0x4000>;
			fsl,mux_mask = <0x7>;
		};

		anatop: anatop@400d8000 {
			compatible = "fsl,imxrt-anatop";
			reg = <0x400d8000 0x4000>;
		};

		clks: clock-controller@400fc000 {
			compatible = "fsl,imxrt1050-ccm";
			reg = <0x400fc000 0x4000>;
			interrupts = <95>, <96>;
			clocks = <&osc>;
			clock-names = "osc";
			#clock-cells = <1>;
			assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
				<&clks IMXRT1050_CLK_PLL1_BYPASS>,
				<&clks IMXRT1050_CLK_PLL2_BYPASS>,
				<&clks IMXRT1050_CLK_PLL3_BYPASS>,
				<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
				<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
			assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
				<&clks IMXRT1050_CLK_PLL1_ARM>,
				<&clks IMXRT1050_CLK_PLL2_SYS>,
				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
				<&clks IMXRT1050_CLK_PLL2_SYS>;
		};

		edma1: dma-controller@400e8000 {
			#dma-cells = <2>;
			compatible = "fsl,imx7ulp-edma";
			reg = <0x400e8000 0x4000>,
				<0x400ec000 0x4000>;
			dma-channels = <32>;
			interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
				<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
			clock-names = "dma", "dmamux0";
			clocks = <&clks IMXRT1050_CLK_DMA>,
				 <&clks IMXRT1050_CLK_DMA_MUX>;
		};

		usdhc1: mmc@402c0000 {
			compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
			reg = <0x402c0000 0x4000>;
			interrupts = <110>;
			clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
				<&clks IMXRT1050_CLK_OSC>,
				<&clks IMXRT1050_CLK_USDHC1>;
			clock-names = "ipg", "ahb", "per";
			bus-width = <4>;
			fsl,wp-controller;
			no-1-8-v;
			max-frequency = <200000000>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step = <2>;
			status = "disabled";
		};

		gpio1: gpio@401b8000 {
			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
			reg = <0x401b8000 0x4000>;
			interrupts = <80>, <81>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@401bc000 {
			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
			reg = <0x401bc000 0x4000>;
			interrupts = <82>, <83>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@401c0000 {
			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
			reg = <0x401c0000 0x4000>;
			interrupts = <84>, <85>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@401c4000 {
			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
			reg = <0x401c4000 0x4000>;
			interrupts = <86>, <87>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@400c0000 {
			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
			reg = <0x400c0000 0x4000>;
			interrupts = <88>, <89>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpt: timer@401ec000 {
			compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
			reg = <0x401ec000 0x4000>;
			interrupts = <100>;
			clocks = <&osc3M>;
			clock-names = "per";
		};
	};
};