| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for NXP Layerscape-1012A family SoC. |
| * |
| * Copyright 2016 Freescale Semiconductor, Inc. |
| * Copyright 2019-2020 NXP |
| * |
| */ |
| |
| #include <dt-bindings/clock/fsl,qoriq-clockgen.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| compatible = "fsl,ls1012a"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| crypto = &crypto; |
| rtc1 = &ftm_alarm0; |
| rtic-a = &rtic_a; |
| rtic-b = &rtic_b; |
| rtic-c = &rtic_c; |
| rtic-d = &rtic_d; |
| sec-mon = &sec_mon; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
| #cooling-cells = <2>; |
| cpu-idle-states = <&CPU_PH20>; |
| }; |
| }; |
| |
| idle-states { |
| /* |
| * PSCI node is not added default, U-boot will add missing |
| * parts if it determines to use PSCI. |
| */ |
| entry-method = "psci"; |
| |
| CPU_PH20: cpu-ph20 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "PH20"; |
| arm,psci-suspend-param = <0x0>; |
| entry-latency-us = <1000>; |
| exit-latency-us = <1000>; |
| min-residency-us = <3000>; |
| }; |
| }; |
| |
| sysclk: sysclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <125000000>; |
| clock-output-names = "sysclk"; |
| }; |
| |
| coreclk: coreclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| clock-output-names = "coreclk"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ |
| <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ |
| <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ |
| <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gic: interrupt-controller@1400000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x1401000 0 0x1000>, /* GICD */ |
| <0x0 0x1402000 0 0x2000>, /* GICC */ |
| <0x0 0x1404000 0 0x2000>, /* GICH */ |
| <0x0 0x1406000 0 0x2000>; /* GICV */ |
| interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| reboot { |
| compatible = "syscon-reboot"; |
| regmap = <&dcfg>; |
| offset = <0xb0>; |
| mask = <0x02>; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <1000>; |
| polling-delay = <5000>; |
| thermal-sensors = <&tmu 0>; |
| |
| trips { |
| cpu_alert: cpu-alert { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit: cpu-crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu0 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| qspi: spi@1550000 { |
| compatible = "fsl,ls1021a-qspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x1550000 0x0 0x10000>, |
| <0x0 0x40000000 0x0 0x10000000>; |
| reg-names = "QuadSPI", "QuadSPI-memory"; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "qspi_en", "qspi"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| status = "disabled"; |
| }; |
| |
| esdhc0: esdhc@1560000 { |
| compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x1560000 0x0 0x10000>; |
| interrupts = <0 62 0x4>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| big-endian; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| scfg: scfg@1570000 { |
| compatible = "fsl,ls1012a-scfg", "syscon"; |
| reg = <0x0 0x1570000 0x0 0x10000>; |
| big-endian; |
| }; |
| |
| esdhc1: esdhc@1580000 { |
| compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x1580000 0x0 0x10000>; |
| interrupts = <0 65 0x4>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| big-endian; |
| broken-cd; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| crypto: crypto@1700000 { |
| compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", |
| "fsl,sec-v4.0"; |
| fsl,sec-era = <8>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x1700000 0x100000>; |
| reg = <0x00 0x1700000 0x0 0x100000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| dma-coherent; |
| |
| sec_jr0: jr@10000 { |
| compatible = "fsl,sec-v5.4-job-ring", |
| "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr1: jr@20000 { |
| compatible = "fsl,sec-v5.4-job-ring", |
| "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x20000 0x10000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr2: jr@30000 { |
| compatible = "fsl,sec-v5.4-job-ring", |
| "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x30000 0x10000>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr3: jr@40000 { |
| compatible = "fsl,sec-v5.4-job-ring", |
| "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x40000 0x10000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| rtic@60000 { |
| compatible = "fsl,sec-v5.4-rtic", |
| "fsl,sec-v5.0-rtic", |
| "fsl,sec-v4.0-rtic"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x60000 0x100>, <0x60e00 0x18>; |
| ranges = <0x0 0x60100 0x500>; |
| |
| rtic_a: rtic-a@0 { |
| compatible = "fsl,sec-v5.4-rtic-memory", |
| "fsl,sec-v5.0-rtic-memory", |
| "fsl,sec-v4.0-rtic-memory"; |
| reg = <0x00 0x20>, <0x100 0x100>; |
| }; |
| |
| rtic_b: rtic-b@20 { |
| compatible = "fsl,sec-v5.4-rtic-memory", |
| "fsl,sec-v5.0-rtic-memory", |
| "fsl,sec-v4.0-rtic-memory"; |
| reg = <0x20 0x20>, <0x200 0x100>; |
| }; |
| |
| rtic_c: rtic-c@40 { |
| compatible = "fsl,sec-v5.4-rtic-memory", |
| "fsl,sec-v5.0-rtic-memory", |
| "fsl,sec-v4.0-rtic-memory"; |
| reg = <0x40 0x20>, <0x300 0x100>; |
| }; |
| |
| rtic_d: rtic-d@60 { |
| compatible = "fsl,sec-v5.4-rtic-memory", |
| "fsl,sec-v5.0-rtic-memory", |
| "fsl,sec-v4.0-rtic-memory"; |
| reg = <0x60 0x20>, <0x400 0x100>; |
| }; |
| }; |
| }; |
| |
| sfp: efuse@1e80000 { |
| compatible = "fsl,ls1021a-sfp"; |
| reg = <0x0 0x1e80000 0x0 0x10000>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| clock-names = "sfp"; |
| }; |
| |
| sec_mon: sec_mon@1e90000 { |
| compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", |
| "fsl,sec-v4.0-mon"; |
| reg = <0x0 0x1e90000 0x0 0x10000>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| dcfg: dcfg@1ee0000 { |
| compatible = "fsl,ls1012a-dcfg", |
| "syscon"; |
| reg = <0x0 0x1ee0000 0x0 0x1000>; |
| big-endian; |
| }; |
| |
| clockgen: clocking@1ee1000 { |
| compatible = "fsl,ls1012a-clockgen"; |
| reg = <0x0 0x1ee1000 0x0 0x1000>; |
| #clock-cells = <2>; |
| clocks = <&sysclk &coreclk>; |
| clock-names = "sysclk", "coreclk"; |
| }; |
| |
| tmu: tmu@1f00000 { |
| compatible = "fsl,qoriq-tmu"; |
| reg = <0x0 0x1f00000 0x0 0x10000>; |
| interrupts = <0 33 0x4>; |
| fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; |
| fsl,tmu-calibration = |
| <0x00000000 0x00000025>, |
| <0x00000001 0x0000002c>, |
| <0x00000002 0x00000032>, |
| <0x00000003 0x00000039>, |
| <0x00000004 0x0000003f>, |
| <0x00000005 0x00000046>, |
| <0x00000006 0x0000004c>, |
| <0x00000007 0x00000053>, |
| <0x00000008 0x00000059>, |
| <0x00000009 0x0000005f>, |
| <0x0000000a 0x00000066>, |
| <0x0000000b 0x0000006c>, |
| |
| <0x00010000 0x00000026>, |
| <0x00010001 0x0000002d>, |
| <0x00010002 0x00000035>, |
| <0x00010003 0x0000003d>, |
| <0x00010004 0x00000045>, |
| <0x00010005 0x0000004d>, |
| <0x00010006 0x00000055>, |
| <0x00010007 0x0000005d>, |
| <0x00010008 0x00000065>, |
| <0x00010009 0x0000006d>, |
| |
| <0x00020000 0x00000026>, |
| <0x00020001 0x00000030>, |
| <0x00020002 0x0000003a>, |
| <0x00020003 0x00000044>, |
| <0x00020004 0x0000004e>, |
| <0x00020005 0x00000059>, |
| <0x00020006 0x00000063>, |
| |
| <0x00030000 0x00000014>, |
| <0x00030001 0x00000021>, |
| <0x00030002 0x0000002e>, |
| <0x00030003 0x0000003a>, |
| <0x00030004 0x00000047>, |
| <0x00030005 0x00000053>, |
| <0x00030006 0x00000060>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| i2c0: i2c@2180000 { |
| compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2180000 0x0 0x10000>; |
| interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| scl-gpios = <&gpio0 2 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@2190000 { |
| compatible = "fsl,ls1012a-i2c", "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2190000 0x0 0x10000>; |
| interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| scl-gpios = <&gpio0 13 0>; |
| status = "disabled"; |
| }; |
| |
| dspi: spi@2100000 { |
| compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2100000 0x0 0x10000>; |
| interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "dspi"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| spi-num-chipselects = <5>; |
| big-endian; |
| status = "disabled"; |
| }; |
| |
| duart0: serial@21c0500 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x00 0x21c0500 0x0 0x100>; |
| interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| status = "disabled"; |
| }; |
| |
| duart1: serial@21c0600 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x00 0x21c0600 0x0 0x100>; |
| interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@2300000 { |
| compatible = "fsl,qoriq-gpio"; |
| reg = <0x0 0x2300000 0x0 0x10000>; |
| interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio1: gpio@2310000 { |
| compatible = "fsl,qoriq-gpio"; |
| reg = <0x0 0x2310000 0x0 0x10000>; |
| interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| wdog0: watchdog@2ad0000 { |
| compatible = "fsl,ls1012a-wdt", |
| "fsl,imx21-wdt"; |
| reg = <0x0 0x2ad0000 0x0 0x10000>; |
| interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; |
| big-endian; |
| }; |
| |
| sai1: sai@2b50000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0x2b50000 0x0 0x10000>; |
| interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 47>, |
| <&edma0 1 46>; |
| status = "disabled"; |
| }; |
| |
| sai2: sai@2b60000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0x2b60000 0x0 0x10000>; |
| interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 45>, |
| <&edma0 1 44>; |
| status = "disabled"; |
| }; |
| |
| edma0: dma-controller@2c00000 { |
| #dma-cells = <2>; |
| compatible = "fsl,vf610-edma"; |
| reg = <0x0 0x2c00000 0x0 0x10000>, |
| <0x0 0x2c10000 0x0 0x10000>, |
| <0x0 0x2c20000 0x0 0x10000>; |
| interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, |
| <0 103 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-tx", "edma-err"; |
| dma-channels = <32>; |
| big-endian; |
| clock-names = "dmamux0", "dmamux1"; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>, |
| <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(4)>; |
| }; |
| |
| usb0: usb@2f00000 { |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x2f00000 0x0 0x10000>; |
| interrupts = <0 60 0x4>; |
| dr_mode = "host"; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,dis_rxdet_inp3_quirk; |
| snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
| snps,host-vbus-glitches; |
| }; |
| |
| sata: sata@3200000 { |
| compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; |
| reg = <0x0 0x3200000 0x0 0x10000>, |
| <0x0 0x20140520 0x0 0x4>; |
| reg-names = "ahci", "sata-ecc"; |
| interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
| QORIQ_CLK_PLL_DIV(1)>; |
| dma-coherent; |
| status = "disabled"; |
| }; |
| |
| usb1: usb@8600000 { |
| compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; |
| reg = <0x0 0x8600000 0x0 0x1000>; |
| interrupts = <0 139 0x4>; |
| dr_mode = "host"; |
| phy_type = "ulpi"; |
| }; |
| |
| msi: msi-controller1@1572000 { |
| compatible = "fsl,ls1012a-msi"; |
| reg = <0x0 0x1572000 0x0 0x8>; |
| msi-controller; |
| interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie1: pcie@3400000 { |
| compatible = "fsl,ls1012a-pcie"; |
| reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ |
| <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| interrupts = <0 118 0x4>, /* controller interrupt */ |
| <0 117 0x4>; /* PME interrupt */ |
| interrupt-names = "aer", "pme"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| num-viewport = <2>; |
| bus-range = <0x0 0xff>; |
| ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ |
| 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
| msi-parent = <&msi>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; |
| big-endian; |
| status = "disabled"; |
| }; |
| |
| rcpm: power-controller@1ee2140 { |
| compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; |
| reg = <0x0 0x1ee2140 0x0 0x4>; |
| #fsl,rcpm-wakeup-cells = <1>; |
| }; |
| |
| ftm_alarm0: timer@29d0000 { |
| compatible = "fsl,ls1012a-ftm-alarm"; |
| reg = <0x0 0x29d0000 0x0 0x10000>; |
| fsl,rcpm-wakeup = <&rcpm 0x20000>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| big-endian; |
| }; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| }; |
| }; |
