| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2022 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx93.dtsi" |
| |
| / { |
| model = "NXP i.MX93 11X11 EVK board"; |
| compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; |
| |
| chosen { |
| stdout-path = &lpuart1; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| alloc-ranges = <0 0x80000000 0 0x40000000>; |
| size = <0 0x10000000>; |
| linux,cma-default; |
| }; |
| |
| vdev0vring0: vdev0vring0@a4000000 { |
| reg = <0 0xa4000000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdev0vring1: vdev0vring1@a4008000 { |
| reg = <0 0xa4008000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdev1vring0: vdev1vring0@a4000000 { |
| reg = <0 0xa4010000 0 0x8000>; |
| no-map; |
| }; |
| |
| vdev1vring1: vdev1vring1@a4018000 { |
| reg = <0 0xa4018000 0 0x8000>; |
| no-map; |
| }; |
| |
| rsc_table: rsc-table@2021f000 { |
| reg = <0 0x2021f000 0 0x1000>; |
| no-map; |
| }; |
| |
| vdevbuffer: vdevbuffer@a4020000 { |
| compatible = "shared-dma-pool"; |
| reg = <0 0xa4020000 0 0x100000>; |
| no-map; |
| }; |
| |
| }; |
| |
| reg_vref_1v8: regulator-adc-vref { |
| compatible = "regulator-fixed"; |
| regulator-name = "vref_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; |
| off-on-delay-us = <12000>; |
| enable-active-high; |
| }; |
| }; |
| |
| &adc1 { |
| vref-supply = <®_vref_1v8>; |
| status = "okay"; |
| }; |
| |
| &cm33 { |
| mbox-names = "tx", "rx", "rxdb"; |
| mboxes = <&mu1 0 1>, |
| <&mu1 1 1>, |
| <&mu1 3 1>; |
| memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, |
| <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; |
| status = "okay"; |
| }; |
| |
| &mu1 { |
| status = "okay"; |
| }; |
| |
| &mu2 { |
| status = "okay"; |
| }; |
| |
| &eqos { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_eqos>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy1>; |
| status = "okay"; |
| |
| mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <5000000>; |
| |
| ethphy1: ethernet-phy@1 { |
| reg = <1>; |
| eee-broken-1000t; |
| }; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy2>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <5000000>; |
| |
| ethphy2: ethernet-phy@2 { |
| reg = <2>; |
| eee-broken-1000t; |
| }; |
| }; |
| }; |
| |
| &lpuart1 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &lpuart5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart5>; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1>; |
| pinctrl-2 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| bus-width = <4>; |
| status = "okay"; |
| no-sdio; |
| no-mmc; |
| }; |
| |
| &wdog3 { |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_eqos: eqosgrp { |
| fsl,pins = < |
| MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e |
| MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e |
| MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e |
| MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e |
| MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e |
| MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e |
| MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe |
| MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e |
| MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e |
| MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e |
| MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e |
| MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e |
| MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe |
| MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e |
| >; |
| }; |
| |
| pinctrl_fec: fecgrp { |
| fsl,pins = < |
| MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e |
| MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e |
| MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e |
| MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e |
| MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e |
| MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e |
| MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe |
| MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e |
| MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e |
| MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e |
| MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e |
| MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e |
| MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe |
| MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX93_PAD_UART1_RXD__LPUART1_RX 0x31e |
| MX93_PAD_UART1_TXD__LPUART1_TX 0x31e |
| >; |
| }; |
| |
| pinctrl_uart5: uart5grp { |
| fsl,pins = < |
| MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e |
| MX93_PAD_DAP_TDI__LPUART5_RX 0x31e |
| MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e |
| MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e |
| >; |
| }; |
| |
| /* need to config the SION for data and cmd pad, refer to ERR052021 */ |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe |
| MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe |
| MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe |
| MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe |
| MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe |
| MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe |
| MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe |
| MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe |
| MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe |
| MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe |
| MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe |
| >; |
| }; |
| |
| pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { |
| fsl,pins = < |
| MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2gpiogrp { |
| fsl,pins = < |
| MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e |
| >; |
| }; |
| |
| /* need to config the SION for data and cmd pad, refer to ERR052021 */ |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe |
| MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe |
| MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe |
| MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe |
| MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe |
| MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe |
| MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| }; |
