| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2015 MediaTek Inc. |
| * Copyright (C) 2023 Collabora Ltd. |
| * Authors: Mars.C <mars.cheng@mediatek.com> |
| * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/mediatek,mt6795-clk.h> |
| #include <dt-bindings/gce/mediatek,mt6795-gce.h> |
| #include <dt-bindings/memory/mt6795-larb-port.h> |
| #include <dt-bindings/pinctrl/mt6795-pinfunc.h> |
| #include <dt-bindings/power/mt6795-power.h> |
| #include <dt-bindings/reset/mediatek,mt6795-resets.h> |
| |
| / { |
| compatible = "mediatek,mt6795"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| ovl0 = &ovl0; |
| ovl1 = &ovl1; |
| rdma0 = &rdma0; |
| rdma1 = &rdma1; |
| rdma2 = &rdma2; |
| wdma0 = &wdma0; |
| wdma1 = &wdma1; |
| color0 = &color0; |
| color1 = &color1; |
| split0 = &split0; |
| split1 = &split1; |
| dpi0 = &dpi0; |
| dsi0 = &dsi0; |
| dsi1 = &dsi1; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x000>; |
| cci-control-port = <&cci_control2>; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x001>; |
| cci-control-port = <&cci_control2>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x002>; |
| cci-control-port = <&cci_control2>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x003>; |
| cci-control-port = <&cci_control2>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_0>; |
| }; |
| |
| cpu4: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x100>; |
| cci-control-port = <&cci_control1>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_1>; |
| }; |
| |
| cpu5: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x101>; |
| cci-control-port = <&cci_control1>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_1>; |
| }; |
| |
| cpu6: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x102>; |
| cci-control-port = <&cci_control1>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_1>; |
| }; |
| |
| cpu7: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x103>; |
| cci-control-port = <&cci_control1>; |
| i-cache-size = <32768>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <32768>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l2_1>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| l2_0: l2-cache0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| |
| l2_1: l2-cache1 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-size = <1048576>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| cache-unified; |
| }; |
| }; |
| |
| clk26m: oscillator-26m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| clk32k: oscillator-32k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32000>; |
| clock-output-names = "clk32k"; |
| }; |
| |
| system_clk: dummy13m { |
| compatible = "fixed-clock"; |
| clock-frequency = <13000000>; |
| #clock-cells = <0>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| topckgen: syscon@10000000 { |
| compatible = "mediatek,mt6795-topckgen", "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: syscon@10001000 { |
| compatible = "mediatek,mt6795-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| pericfg: syscon@10003000 { |
| compatible = "mediatek,mt6795-pericfg", "syscon"; |
| reg = <0 0x10003000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| scpsys: syscon@10006000 { |
| compatible = "syscon", "simple-mfd"; |
| reg = <0 0x10006000 0 0x1000>; |
| #power-domain-cells = <1>; |
| |
| /* System Power Manager */ |
| spm: power-controller { |
| compatible = "mediatek,mt6795-power-controller"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| /* power domains of the SoC */ |
| power-domain@MT6795_POWER_DOMAIN_VDEC { |
| reg = <MT6795_POWER_DOMAIN_VDEC>; |
| clocks = <&topckgen CLK_TOP_MM_SEL>; |
| clock-names = "mm"; |
| #power-domain-cells = <0>; |
| }; |
| power-domain@MT6795_POWER_DOMAIN_VENC { |
| reg = <MT6795_POWER_DOMAIN_VENC>; |
| clocks = <&topckgen CLK_TOP_MM_SEL>, |
| <&topckgen CLK_TOP_VENC_SEL>; |
| clock-names = "mm", "venc"; |
| #power-domain-cells = <0>; |
| }; |
| power-domain@MT6795_POWER_DOMAIN_ISP { |
| reg = <MT6795_POWER_DOMAIN_ISP>; |
| clocks = <&topckgen CLK_TOP_MM_SEL>; |
| clock-names = "mm"; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT6795_POWER_DOMAIN_MM { |
| reg = <MT6795_POWER_DOMAIN_MM>; |
| clocks = <&topckgen CLK_TOP_MM_SEL>; |
| clock-names = "mm"; |
| #power-domain-cells = <0>; |
| mediatek,infracfg = <&infracfg>; |
| }; |
| |
| power-domain@MT6795_POWER_DOMAIN_MJC { |
| reg = <MT6795_POWER_DOMAIN_MJC>; |
| clocks = <&topckgen CLK_TOP_MM_SEL>, |
| <&topckgen CLK_TOP_MJC_SEL>; |
| clock-names = "mm", "mjc"; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@MT6795_POWER_DOMAIN_AUDIO { |
| reg = <MT6795_POWER_DOMAIN_AUDIO>; |
| #power-domain-cells = <0>; |
| }; |
| |
| mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { |
| reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; |
| clocks = <&clk26m>; |
| clock-names = "mfg"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT6795_POWER_DOMAIN_MFG_2D { |
| reg = <MT6795_POWER_DOMAIN_MFG_2D>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #power-domain-cells = <1>; |
| |
| power-domain@MT6795_POWER_DOMAIN_MFG { |
| reg = <MT6795_POWER_DOMAIN_MFG>; |
| #power-domain-cells = <0>; |
| mediatek,infracfg = <&infracfg>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| pio: pinctrl@10005000 { |
| compatible = "mediatek,mt6795-pinctrl"; |
| reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; |
| reg-names = "base", "eint"; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 196>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| watchdog: watchdog@10007000 { |
| compatible = "mediatek,mt6795-wdt"; |
| reg = <0 0x10007000 0 0x100>; |
| interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; |
| #reset-cells = <1>; |
| timeout-sec = <20>; |
| }; |
| |
| timer: timer@10008000 { |
| compatible = "mediatek,mt6795-timer", |
| "mediatek,mt6577-timer"; |
| reg = <0 0x10008000 0 0x1000>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&system_clk>, <&clk32k>; |
| }; |
| |
| pwrap: pwrap@1000d000 { |
| compatible = "mediatek,mt6795-pwrap"; |
| reg = <0 0x1000d000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
| resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>; |
| reset-names = "pwrap"; |
| clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>; |
| clock-names = "spi", "wrap"; |
| }; |
| |
| sysirq: intpol-controller@10200620 { |
| compatible = "mediatek,mt6795-sysirq", |
| "mediatek,mt6577-sysirq"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x10200620 0 0x20>; |
| }; |
| |
| systimer: timer@10200670 { |
| compatible = "mediatek,mt6795-systimer"; |
| reg = <0 0x10200670 0 0x10>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&system_clk>; |
| clock-names = "clk13m"; |
| }; |
| |
| iommu: iommu@10205000 { |
| compatible = "mediatek,mt6795-m4u"; |
| reg = <0 0x10205000 0 0x1000>; |
| clocks = <&infracfg CLK_INFRA_M4U>; |
| clock-names = "bclk"; |
| interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; |
| mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| #iommu-cells = <1>; |
| }; |
| |
| apmixedsys: syscon@10209000 { |
| compatible = "mediatek,mt6795-apmixedsys", "syscon"; |
| reg = <0 0x10209000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| fhctl: clock-controller@10209f00 { |
| compatible = "mediatek,mt6795-fhctl"; |
| reg = <0 0x10209f00 0 0x100>; |
| status = "disabled"; |
| }; |
| |
| gce: mailbox@10212000 { |
| compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; |
| reg = <0 0x10212000 0 0x1000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_GCE>; |
| clock-names = "gce"; |
| #mbox-cells = <2>; |
| }; |
| |
| mipi_tx0: dsi-phy@10215000 { |
| compatible = "mediatek,mt8173-mipi-tx"; |
| reg = <0 0x10215000 0 0x1000>; |
| clocks = <&clk26m>; |
| clock-output-names = "mipi_tx0_pll"; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| mipi_tx1: dsi-phy@10216000 { |
| compatible = "mediatek,mt8173-mipi-tx"; |
| reg = <0 0x10216000 0 0x1000>; |
| clocks = <&clk26m>; |
| clock-output-names = "mipi_tx1_pll"; |
| #clock-cells = <0>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@10221000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x10221000 0 0x1000>, |
| <0 0x10222000 0 0x2000>, |
| <0 0x10224000 0 0x2000>, |
| <0 0x10226000 0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| cci: cci@10390000 { |
| compatible = "arm,cci-400"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0 0x10390000 0 0x1000>; |
| ranges = <0 0 0x10390000 0x10000>; |
| |
| cci_control0: slave-if@1000 { |
| compatible = "arm,cci-400-ctrl-if"; |
| interface-type = "ace-lite"; |
| reg = <0x1000 0x1000>; |
| }; |
| |
| cci_control1: slave-if@4000 { |
| compatible = "arm,cci-400-ctrl-if"; |
| interface-type = "ace"; |
| reg = <0x4000 0x1000>; |
| }; |
| |
| cci_control2: slave-if@5000 { |
| compatible = "arm,cci-400-ctrl-if"; |
| interface-type = "ace"; |
| reg = <0x5000 0x1000>; |
| }; |
| |
| pmu@9000 { |
| compatible = "arm,cci-400-pmu,r1"; |
| reg = <0x9000 0x5000>; |
| interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt6795-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x400>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 0>, <&apdma 1>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt6795-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x400>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 2>, <&apdma 3>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| apdma: dma-controller@11000380 { |
| compatible = "mediatek,mt6795-uart-dma", |
| "mediatek,mt6577-uart-dma"; |
| reg = <0 0x11000380 0 0x60>, |
| <0 0x11000400 0 0x60>, |
| <0 0x11000480 0 0x60>, |
| <0 0x11000500 0 0x60>, |
| <0 0x11000580 0 0x60>, |
| <0 0x11000600 0 0x60>, |
| <0 0x11000680 0 0x60>, |
| <0 0x11000700 0 0x60>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; |
| dma-requests = <8>; |
| clocks = <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "apdma"; |
| mediatek,dma-33bits; |
| #dma-cells = <1>; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt6795-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x400>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 4>, <&apdma 5>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@11005000 { |
| compatible = "mediatek,mt6795-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11005000 0 0x400>; |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; |
| clock-names = "baud", "bus"; |
| dmas = <&apdma 6>, <&apdma 7>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| pwm2: pwm@11006000 { |
| compatible = "mediatek,mt6795-pwm"; |
| reg = <0 0x11006000 0 0x1000>; |
| #pwm-cells = <2>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_PWM_SEL>, |
| <&pericfg CLK_PERI_PWM>, |
| <&pericfg CLK_PERI_PWM1>, |
| <&pericfg CLK_PERI_PWM2>, |
| <&pericfg CLK_PERI_PWM3>, |
| <&pericfg CLK_PERI_PWM4>, |
| <&pericfg CLK_PERI_PWM5>, |
| <&pericfg CLK_PERI_PWM6>, |
| <&pericfg CLK_PERI_PWM7>; |
| clock-names = "top", "main", "pwm1", "pwm2", "pwm3", |
| "pwm4", "pwm5", "pwm6", "pwm7"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11007000 { |
| compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; |
| reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11008000 { |
| compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; |
| reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@11009000 { |
| compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; |
| reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@11010000 { |
| compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; |
| reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@11011000 { |
| compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; |
| reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; |
| clock-div = <16>; |
| clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| mmc0: mmc@11230000 { |
| compatible = "mediatek,mt6795-mmc"; |
| reg = <0 0x11230000 0 0x1000>; |
| interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_0>, |
| <&topckgen CLK_TOP_MSDC50_0_H_SEL>, |
| <&topckgen CLK_TOP_MSDC50_0_SEL>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@11240000 { |
| compatible = "mediatek,mt6795-mmc"; |
| reg = <0 0x11240000 0 0x1000>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_1>, |
| <&topckgen CLK_TOP_AXI_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmc2: mmc@11250000 { |
| compatible = "mediatek,mt6795-mmc"; |
| reg = <0 0x11250000 0 0x1000>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_2>, |
| <&topckgen CLK_TOP_AXI_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmc3: mmc@11260000 { |
| compatible = "mediatek,mt6795-mmc"; |
| reg = <0 0x11260000 0 0x1000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&pericfg CLK_PERI_MSDC30_3>, |
| <&topckgen CLK_TOP_AXI_SEL>; |
| clock-names = "source", "hclk"; |
| status = "disabled"; |
| }; |
| |
| mmsys: syscon@14000000 { |
| compatible = "mediatek,mt6795-mmsys", "syscon"; |
| reg = <0 0x14000000 0 0x1000>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; |
| assigned-clock-rates = <400000000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, |
| <&gce 1 CMDQ_THR_PRIO_HIGHEST>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; |
| }; |
| |
| ovl0: ovl@1400c000 { |
| compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; |
| reg = <0 0x1400c000 0 0x1000>; |
| interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_OVL0>; |
| iommus = <&iommu M4U_PORT_DISP_OVL0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; |
| }; |
| |
| ovl1: ovl@1400d000 { |
| compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; |
| reg = <0 0x1400d000 0 0x1000>; |
| interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_OVL1>; |
| iommus = <&iommu M4U_PORT_DISP_OVL1>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; |
| }; |
| |
| rdma0: rdma@1400e000 { |
| compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; |
| reg = <0 0x1400e000 0 0x1000>; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA0>; |
| iommus = <&iommu M4U_PORT_DISP_RDMA0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; |
| }; |
| |
| rdma1: rdma@1400f000 { |
| compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; |
| reg = <0 0x1400f000 0 0x1000>; |
| interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA1>; |
| iommus = <&iommu M4U_PORT_DISP_RDMA1>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; |
| }; |
| |
| rdma2: rdma@14010000 { |
| compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; |
| reg = <0 0x14010000 0 0x1000>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_RDMA2>; |
| iommus = <&iommu M4U_PORT_DISP_RDMA2>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; |
| }; |
| |
| wdma0: wdma@14011000 { |
| compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; |
| reg = <0 0x14011000 0 0x1000>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_WDMA0>; |
| iommus = <&iommu M4U_PORT_DISP_WDMA0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; |
| }; |
| |
| wdma1: wdma@14012000 { |
| compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; |
| reg = <0 0x14012000 0 0x1000>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_WDMA1>; |
| iommus = <&iommu M4U_PORT_DISP_WDMA1>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; |
| }; |
| |
| color0: color@14013000 { |
| compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; |
| reg = <0 0x14013000 0 0x1000>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_COLOR0>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; |
| }; |
| |
| color1: color@14014000 { |
| compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; |
| reg = <0 0x14014000 0 0x1000>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_COLOR1>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; |
| }; |
| |
| aal@14015000 { |
| compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal"; |
| reg = <0 0x14015000 0 0x1000>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_AAL>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; |
| }; |
| |
| gamma@14016000 { |
| compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma"; |
| reg = <0 0x14016000 0 0x1000>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_GAMMA>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; |
| }; |
| |
| merge@14017000 { |
| compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge"; |
| reg = <0 0x14017000 0 0x1000>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_MERGE>; |
| }; |
| |
| split0: split@14018000 { |
| compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; |
| reg = <0 0x14018000 0 0x1000>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_SPLIT0>; |
| }; |
| |
| split1: split@14019000 { |
| compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; |
| reg = <0 0x14019000 0 0x1000>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_SPLIT1>; |
| }; |
| |
| ufoe@1401a000 { |
| compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe"; |
| reg = <0 0x1401a000 0 0x1000>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DISP_UFOE>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; |
| }; |
| |
| dsi0: dsi@1401b000 { |
| compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; |
| reg = <0 0x1401b000 0 0x1000>; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DSI0_ENGINE>, |
| <&mmsys CLK_MM_DSI0_DIGITAL>, |
| <&mipi_tx0>; |
| clock-names = "engine", "digital", "hs"; |
| phys = <&mipi_tx0>; |
| phy-names = "dphy"; |
| status = "disabled"; |
| }; |
| |
| dsi1: dsi@1401c000 { |
| compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; |
| reg = <0 0x1401c000 0 0x1000>; |
| interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DSI1_ENGINE>, |
| <&mmsys CLK_MM_DSI1_DIGITAL>, |
| <&mipi_tx1>; |
| clock-names = "engine", "digital", "hs"; |
| phys = <&mipi_tx1>; |
| phy-names = "dphy"; |
| status = "disabled"; |
| }; |
| |
| dpi0: dpi@1401d000 { |
| compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi"; |
| reg = <0 0x1401d000 0 0x1000>; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_DPI_PIXEL>, |
| <&mmsys CLK_MM_DPI_ENGINE>, |
| <&apmixedsys CLK_APMIXED_TVDPLL>; |
| clock-names = "pixel", "engine", "pll"; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@1401e000 { |
| compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; |
| reg = <0 0x1401e000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; |
| clock-names = "main", "mm"; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@1401f000 { |
| compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; |
| reg = <0 0x1401f000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>; |
| clock-names = "main", "mm"; |
| status = "disabled"; |
| }; |
| |
| mutex: mutex@14020000 { |
| compatible = "mediatek,mt8173-disp-mutex"; |
| reg = <0 0x14020000 0 0x1000>; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&mmsys CLK_MM_MUTEX_32K>; |
| mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, |
| <CMDQ_EVENT_MUTEX1_STREAM_EOF>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; |
| }; |
| |
| larb0: larb@14021000 { |
| compatible = "mediatek,mt6795-smi-larb"; |
| reg = <0 0x14021000 0 0x1000>; |
| clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; |
| clock-names = "apb", "smi"; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <0>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| }; |
| |
| smi_common: smi@14022000 { |
| compatible = "mediatek,mt6795-smi-common"; |
| reg = <0 0x14022000 0 0x1000>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_MM>; |
| clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; |
| clock-names = "apb", "smi"; |
| }; |
| |
| od@14023000 { |
| compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od"; |
| reg = <0 0x14023000 0 0x1000>; |
| clocks = <&mmsys CLK_MM_DISP_OD>; |
| mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; |
| }; |
| |
| larb2: larb@15001000 { |
| compatible = "mediatek,mt6795-smi-larb"; |
| reg = <0 0x15001000 0 0x1000>; |
| clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; |
| clock-names = "apb", "smi"; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <2>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; |
| }; |
| |
| vdecsys: clock-controller@16000000 { |
| compatible = "mediatek,mt6795-vdecsys"; |
| reg = <0 0x16000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb1: larb@16010000 { |
| compatible = "mediatek,mt6795-smi-larb"; |
| reg = <0 0x16010000 0 0x1000>; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <1>; |
| clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; |
| clock-names = "apb", "smi"; |
| power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; |
| }; |
| |
| vencsys: clock-controller@18000000 { |
| compatible = "mediatek,mt6795-vencsys"; |
| reg = <0 0x18000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| larb3: larb@18001000 { |
| compatible = "mediatek,mt6795-smi-larb"; |
| reg = <0 0x18001000 0 0x1000>; |
| clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; |
| clock-names = "apb", "smi"; |
| mediatek,smi = <&smi_common>; |
| mediatek,larb-id = <3>; |
| power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; |
| }; |
| }; |
| }; |
