| * Spreadtrum SDHCI controller (sdhci-sprd) |
| |
| The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface |
| for MMC, SD and SDIO types of cards. |
| |
| This file documents differences between the core properties in mmc.txt |
| and the properties used by the sdhci-sprd driver. |
| |
| Required properties: |
| - compatible: Should contain "sprd,sdhci-r11". |
| - reg: physical base address of the controller and length. |
| - interrupts: Interrupts used by the SDHCI controller. |
| - clocks: Should contain phandle for the clock feeding the SDHCI controller |
| - clock-names: Should contain the following: |
| "sdio" - SDIO source clock (required) |
| "enable" - gate clock which used for enabling/disabling the device (required) |
| "2x_enable" - gate clock controlling the device for some special platforms (optional) |
| |
| Optional properties: |
| - assigned-clocks: the same with "sdio" clock |
| - assigned-clock-parents: the default parent of "sdio" clock |
| - pinctrl-names: should be "default", "state_uhs" |
| - pinctrl-0: should contain default/high speed pin control |
| - pinctrl-1: should contain uhs mode pin control |
| |
| PHY DLL delays are used to delay the data valid window, and align the window |
| to sampling clock. PHY DLL delays can be configured by following properties, |
| and each property contains 4 cells which are used to configure the clock data |
| write line delay value, clock read command line delay value, clock read data |
| positive edge delay value and clock read data negative edge delay value. |
| Each cell's delay value unit is cycle of the PHY clock. |
| |
| - sprd,phy-delay-legacy: Delay value for legacy timing. |
| - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing. |
| - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing. |
| - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing. |
| - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing. |
| - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing. |
| - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing. |
| - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing. |
| - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing. |
| |
| Examples: |
| |
| sdio0: sdio@20600000 { |
| compatible = "sprd,sdhci-r11"; |
| reg = <0 0x20600000 0 0x1000>; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clock-names = "sdio", "enable"; |
| clocks = <&ap_clk CLK_EMMC_2X>, |
| <&apahb_gate CLK_EMMC_EB>; |
| assigned-clocks = <&ap_clk CLK_EMMC_2X>; |
| assigned-clock-parents = <&rpll CLK_RPLL_390M>; |
| |
| pinctrl-names = "default", "state_uhs"; |
| pinctrl-0 = <&sd0_pins_default>; |
| pinctrl-1 = <&sd0_pins_uhs>; |
| |
| sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>; |
| bus-width = <8>; |
| non-removable; |
| no-sdio; |
| no-sd; |
| cap-mmc-hw-reset; |
| status = "okay"; |
| }; |