Documentation/devicetree/bindings/timer/sifive,clint.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive Core Local Interruptor

maintainers:
  - Palmer Dabbelt <palmer@dabbelt.com>
  - Anup Patel <anup.patel@wdc.com>

description:
  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
  interrupts. It directly connects to the timer and inter-processor interrupt
  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
  interrupt controller is the parent interrupt controller for CLINT device.
  The clock frequency of CLINT is specified via "timebase-frequency" DT
  property of "/cpus" DT node. The "timebase-frequency" DT property is
  described in Documentation/devicetree/bindings/riscv/cpus.yaml

properties:
  compatible:
    items:
      - enum:
          - sifive,fu540-c000-clint
          - starfive,jh7100-clint
          - canaan,k210-clint
      - const: sifive,clint0

    description:
      Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
      Supported compatible strings are -
      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
      onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
      CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
      "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
      integration tweaks.
      Please refer to sifive-blocks-ip-versioning.txt for details

  reg:
    maxItems: 1

  interrupts-extended:
    minItems: 1

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts-extended

examples:
  - |
    timer@2000000 {
      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
      interrupts-extended = <&cpu1intc 3 &cpu1intc 7
                             &cpu2intc 3 &cpu2intc 7
                             &cpu3intc 3 &cpu3intc 7
                             &cpu4intc 3 &cpu4intc 7>;
       reg = <0x2000000 0x10000>;
    };
...