| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| * Based on "omap4.dtsi" |
| */ |
| |
| #include <dt-bindings/bus/ti-sysc.h> |
| #include <dt-bindings/clock/dra7.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/dra.h> |
| #include <dt-bindings/clock/dra7.h> |
| |
| #define MAX_SOURCES 400 |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| compatible = "ti,dra7xx"; |
| interrupt-parent = <&crossbar_mpu>; |
| chosen { }; |
| |
| aliases { |
| i2c0 = &i2c1; |
| i2c1 = &i2c2; |
| i2c2 = &i2c3; |
| i2c3 = &i2c4; |
| i2c4 = &i2c5; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| serial4 = &uart5; |
| serial5 = &uart6; |
| serial6 = &uart7; |
| serial7 = &uart8; |
| serial8 = &uart9; |
| serial9 = &uart10; |
| ethernet0 = &cpsw_port1; |
| ethernet1 = &cpsw_port2; |
| d_can0 = &dcan1; |
| d_can1 = &dcan2; |
| spi0 = &qspi; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| status = "disabled"; /* See ARM architected timer wrap erratum i940 */ |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| gic: interrupt-controller@48211000 { |
| compatible = "arm,cortex-a15-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x0 0x48211000 0x0 0x1000>, |
| <0x0 0x48212000 0x0 0x2000>, |
| <0x0 0x48214000 0x0 0x2000>, |
| <0x0 0x48216000 0x0 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| wakeupgen: interrupt-controller@48281000 { |
| compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x0 0x48281000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| |
| operating-points-v2 = <&cpu0_opp_table>; |
| |
| clocks = <&dpll_mpu_ck>; |
| clock-names = "cpu"; |
| |
| clock-latency = <300000>; /* From omap-cpufreq driver */ |
| |
| /* cooling options */ |
| #cooling-cells = <2>; /* min followed by max */ |
| |
| vbb-supply = <&abb_mpu>; |
| }; |
| }; |
| |
| cpu0_opp_table: opp-table { |
| compatible = "operating-points-v2-ti-cpu"; |
| syscon = <&scm_wkup>; |
| |
| opp_nom-1000000000 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <1060000 850000 1150000>, |
| <1060000 850000 1150000>; |
| opp-supported-hw = <0xFF 0x01>; |
| opp-suspend; |
| }; |
| |
| opp_od-1176000000 { |
| opp-hz = /bits/ 64 <1176000000>; |
| opp-microvolt = <1160000 885000 1160000>, |
| <1160000 885000 1160000>; |
| |
| opp-supported-hw = <0xFF 0x02>; |
| }; |
| |
| opp_high@1500000000 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <1210000 950000 1250000>, |
| <1210000 950000 1250000>; |
| opp-supported-hw = <0xFF 0x04>; |
| }; |
| }; |
| |
| /* |
| * The soc node represents the soc top level view. It is used for IPs |
| * that are not memory mapped in the MPU view or for the MPU itself. |
| */ |
| soc { |
| compatible = "ti,omap-infra"; |
| mpu { |
| compatible = "ti,omap5-mpu"; |
| ti,hwmods = "mpu"; |
| }; |
| }; |
| |
| /* |
| * XXX: Use a flat representation of the SOC interconnect. |
| * The real OMAP interconnect network is quite complex. |
| * Since it will not bring real advantage to represent that in DT for |
| * the moment, just use a fake OCP bus entry to represent the whole bus |
| * hierarchy. |
| */ |
| ocp: ocp { |
| compatible = "ti,dra7-l3-noc", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x0 0xc0000000>; |
| dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; |
| ti,hwmods = "l3_main_1", "l3_main_2"; |
| reg = <0x0 0x44000000 0x0 0x1000000>, |
| <0x0 0x45000000 0x0 0x1000>; |
| interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| |
| l4_cfg: interconnect@4a000000 { |
| }; |
| l4_wkup: interconnect@4ae00000 { |
| }; |
| l4_per1: interconnect@48000000 { |
| }; |
| l4_per2: interconnect@48400000 { |
| }; |
| l4_per3: interconnect@48800000 { |
| }; |
| |
| axi@0 { |
| compatible = "simple-bus"; |
| #size-cells = <1>; |
| #address-cells = <1>; |
| ranges = <0x51000000 0x51000000 0x3000 |
| 0x0 0x20000000 0x10000000>; |
| dma-ranges; |
| /** |
| * To enable PCI endpoint mode, disable the pcie1_rc |
| * node and enable pcie1_ep mode. |
| */ |
| pcie1_rc: pcie@51000000 { |
| reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| reg-names = "rc_dbics", "ti_conf", "config"; |
| interrupts = <0 232 0x4>, <0 233 0x4>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| bus-range = <0x00 0xff>; |
| #interrupt-cells = <1>; |
| num-lanes = <1>; |
| linux,pci-domain = <0>; |
| ti,hwmods = "pcie1"; |
| phys = <&pcie1_phy>; |
| phy-names = "pcie-phy0"; |
| ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| <0 0 0 2 &pcie1_intc 2>, |
| <0 0 0 3 &pcie1_intc 3>, |
| <0 0 0 4 &pcie1_intc 4>; |
| ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; |
| status = "disabled"; |
| pcie1_intc: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| pcie1_ep: pcie_ep@51000000 { |
| reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; |
| reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; |
| interrupts = <0 232 0x4>; |
| num-lanes = <1>; |
| num-ib-windows = <4>; |
| num-ob-windows = <16>; |
| ti,hwmods = "pcie1"; |
| phys = <&pcie1_phy>; |
| phy-names = "pcie-phy0"; |
| ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; |
| ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; |
| status = "disabled"; |
| }; |
| }; |
| |
| axi@1 { |
| compatible = "simple-bus"; |
| #size-cells = <1>; |
| #address-cells = <1>; |
| ranges = <0x51800000 0x51800000 0x3000 |
| 0x0 0x30000000 0x10000000>; |
| dma-ranges; |
| status = "disabled"; |
| pcie2_rc: pcie@51800000 { |
| reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| reg-names = "rc_dbics", "ti_conf", "config"; |
| interrupts = <0 355 0x4>, <0 356 0x4>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| bus-range = <0x00 0xff>; |
| #interrupt-cells = <1>; |
| num-lanes = <1>; |
| linux,pci-domain = <1>; |
| ti,hwmods = "pcie2"; |
| phys = <&pcie2_phy>; |
| phy-names = "pcie-phy0"; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| <0 0 0 2 &pcie2_intc 2>, |
| <0 0 0 3 &pcie2_intc 3>, |
| <0 0 0 4 &pcie2_intc 4>; |
| ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; |
| pcie2_intc: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| }; |
| |
| ocmcram1: ocmcram@40300000 { |
| compatible = "mmio-sram"; |
| reg = <0x40300000 0x80000>; |
| ranges = <0x0 0x40300000 0x80000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| /* |
| * This is a placeholder for an optional reserved |
| * region for use by secure software. The size |
| * of this region is not known until runtime so it |
| * is set as zero to either be updated to reserve |
| * space or left unchanged to leave all SRAM for use. |
| * On HS parts that that require the reserved region |
| * either the bootloader can update the size to |
| * the required amount or the node can be overridden |
| * from the board dts file for the secure platform. |
| */ |
| sram-hs@0 { |
| compatible = "ti,secure-ram"; |
| reg = <0x0 0x0>; |
| }; |
| }; |
| |
| /* |
| * NOTE: ocmcram2 and ocmcram3 are not available on all |
| * DRA7xx and AM57xx variants. Confirm availability in |
| * the data manual for the exact part number in use |
| * before enabling these nodes in the board dts file. |
| */ |
| ocmcram2: ocmcram@40400000 { |
| status = "disabled"; |
| compatible = "mmio-sram"; |
| reg = <0x40400000 0x100000>; |
| ranges = <0x0 0x40400000 0x100000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| ocmcram3: ocmcram@40500000 { |
| status = "disabled"; |
| compatible = "mmio-sram"; |
| reg = <0x40500000 0x100000>; |
| ranges = <0x0 0x40500000 0x100000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| bandgap: bandgap@4a0021e0 { |
| reg = <0x4a0021e0 0xc |
| 0x4a00232c 0xc |
| 0x4a002380 0x2c |
| 0x4a0023C0 0x3c |
| 0x4a002564 0x8 |
| 0x4a002574 0x50>; |
| compatible = "ti,dra752-bandgap"; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| dsp1_system: dsp_system@40d00000 { |
| compatible = "syscon"; |
| reg = <0x40d00000 0x100>; |
| }; |
| |
| dra7_iodelay_core: padconf@4844a000 { |
| compatible = "ti,dra7-iodelay"; |
| reg = <0x4844a000 0x0d1c>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinctrl-cells = <2>; |
| }; |
| |
| target-module@43300000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x43300000 0x4>; |
| reg-names = "rev"; |
| clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x43300000 0x100000>; |
| |
| edma: dma@0 { |
| compatible = "ti,edma3-tpcc"; |
| reg = <0 0x100000>; |
| reg-names = "edma3_cc"; |
| interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma3_ccint", "edma3_mperr", |
| "edma3_ccerrint"; |
| dma-requests = <64>; |
| #dma-cells = <2>; |
| |
| ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; |
| |
| /* |
| * memcpy is disabled, can be enabled with: |
| * ti,edma-memcpy-channels = <20 21>; |
| * for example. Note that these channels need to be |
| * masked in the xbar as well. |
| */ |
| }; |
| }; |
| |
| target-module@43400000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x43400000 0x4>; |
| reg-names = "rev"; |
| clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x43400000 0x100000>; |
| |
| edma_tptc0: dma@0 { |
| compatible = "ti,edma3-tptc"; |
| reg = <0 0x100000>; |
| interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma3_tcerrint"; |
| }; |
| }; |
| |
| target-module@43500000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x43500000 0x4>; |
| reg-names = "rev"; |
| clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x43500000 0x100000>; |
| |
| edma_tptc1: dma@0 { |
| compatible = "ti,edma3-tptc"; |
| reg = <0 0x100000>; |
| interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma3_tcerrint"; |
| }; |
| }; |
| |
| dmm@4e000000 { |
| compatible = "ti,omap5-dmm"; |
| reg = <0x4e000000 0x800>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| ti,hwmods = "dmm"; |
| }; |
| |
| ipu1: ipu@58820000 { |
| compatible = "ti,dra7-ipu"; |
| reg = <0x58820000 0x10000>; |
| reg-names = "l2ram"; |
| iommus = <&mmu_ipu1>; |
| status = "disabled"; |
| resets = <&prm_ipu 0>, <&prm_ipu 1>; |
| clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; |
| firmware-name = "dra7-ipu1-fw.xem4"; |
| }; |
| |
| ipu2: ipu@55020000 { |
| compatible = "ti,dra7-ipu"; |
| reg = <0x55020000 0x10000>; |
| reg-names = "l2ram"; |
| iommus = <&mmu_ipu2>; |
| status = "disabled"; |
| resets = <&prm_core 0>, <&prm_core 1>; |
| clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; |
| firmware-name = "dra7-ipu2-fw.xem4"; |
| }; |
| |
| dsp1: dsp@40800000 { |
| compatible = "ti,dra7-dsp"; |
| reg = <0x40800000 0x48000>, |
| <0x40e00000 0x8000>, |
| <0x40f00000 0x8000>; |
| reg-names = "l2ram", "l1pram", "l1dram"; |
| ti,bootreg = <&scm_conf 0x55c 10>; |
| iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; |
| status = "disabled"; |
| resets = <&prm_dsp1 0>; |
| clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; |
| firmware-name = "dra7-dsp1-fw.xe66"; |
| }; |
| |
| target-module@40d01000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x40d01000 0x4>, |
| <0x40d01010 0x4>, |
| <0x40d01014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; |
| clock-names = "fck"; |
| resets = <&prm_dsp1 1>; |
| reset-names = "rstctrl"; |
| ranges = <0x0 0x40d01000 0x1000>; |
| #size-cells = <1>; |
| #address-cells = <1>; |
| |
| mmu0_dsp1: mmu@0 { |
| compatible = "ti,dra7-dsp-iommu"; |
| reg = <0x0 0x100>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| #iommu-cells = <0>; |
| ti,syscon-mmuconfig = <&dsp1_system 0x0>; |
| }; |
| }; |
| |
| target-module@40d02000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x40d02000 0x4>, |
| <0x40d02010 0x4>, |
| <0x40d02014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; |
| clock-names = "fck"; |
| resets = <&prm_dsp1 1>; |
| reset-names = "rstctrl"; |
| ranges = <0x0 0x40d02000 0x1000>; |
| #size-cells = <1>; |
| #address-cells = <1>; |
| |
| mmu1_dsp1: mmu@0 { |
| compatible = "ti,dra7-dsp-iommu"; |
| reg = <0x0 0x100>; |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| #iommu-cells = <0>; |
| ti,syscon-mmuconfig = <&dsp1_system 0x1>; |
| }; |
| }; |
| |
| target-module@58882000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x58882000 0x4>, |
| <0x58882010 0x4>, |
| <0x58882014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; |
| clock-names = "fck"; |
| resets = <&prm_ipu 2>; |
| reset-names = "rstctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x58882000 0x100>; |
| |
| mmu_ipu1: mmu@0 { |
| compatible = "ti,dra7-iommu"; |
| reg = <0x0 0x100>; |
| interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; |
| #iommu-cells = <0>; |
| ti,iommu-bus-err-back; |
| }; |
| }; |
| |
| target-module@55082000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x55082000 0x4>, |
| <0x55082010 0x4>, |
| <0x55082014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; |
| clock-names = "fck"; |
| resets = <&prm_core 2>; |
| reset-names = "rstctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x55082000 0x100>; |
| |
| mmu_ipu2: mmu@0 { |
| compatible = "ti,dra7-iommu"; |
| reg = <0x0 0x100>; |
| interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; |
| #iommu-cells = <0>; |
| ti,iommu-bus-err-back; |
| }; |
| }; |
| |
| abb_mpu: regulator-abb-mpu { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_mpu"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
| <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
| <0x4ae0c158 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x80>; |
| /* LDOVBBMPU_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBMPU_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 1210000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| abb_ivahd: regulator-abb-ivahd { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_ivahd"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
| <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
| <0x4a002470 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x40000000>; |
| /* LDOVBBIVA_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBIVA_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1250000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| abb_dspeve: regulator-abb-dspeve { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_dspeve"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
| <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
| <0x4a00246c 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x20000000>; |
| /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1250000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| abb_gpu: regulator-abb-gpu { |
| compatible = "ti,abb-v3"; |
| regulator-name = "abb_gpu"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| clocks = <&sys_clkin1>; |
| ti,settling-time = <50>; |
| ti,clock-cycles = <16>; |
| |
| reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
| <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
| <0x4ae0c154 0x4>; |
| reg-names = "setup-address", "control-address", |
| "int-address", "efuse-address", |
| "ldo-address"; |
| ti,tranxdone-status-mask = <0x10000000>; |
| /* LDOVBBGPU_FBB_MUX_CTRL */ |
| ti,ldovbb-override-mask = <0x400>; |
| /* LDOVBBGPU_FBB_VSET_OUT */ |
| ti,ldovbb-vset-mask = <0x1F>; |
| |
| /* |
| * NOTE: only FBB mode used but actual vset will |
| * determine final biasing |
| */ |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 1280000 0 0x8 0 0x02000000 0x01F00000 |
| >; |
| }; |
| |
| qspi: spi@4b300000 { |
| compatible = "ti,dra7xxx-qspi"; |
| reg = <0x4b300000 0x100>, |
| <0x5c000000 0x4000000>; |
| reg-names = "qspi_base", "qspi_mmap"; |
| syscon-chipselects = <&scm_conf 0x558>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| ti,hwmods = "qspi"; |
| clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; |
| clock-names = "fck"; |
| num-cs = <4>; |
| interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| /* OCP2SCP3 */ |
| sata: sata@4a141100 { |
| compatible = "snps,dwc-ahci"; |
| reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&sata_phy>; |
| phy-names = "sata-phy"; |
| clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; |
| ti,hwmods = "sata"; |
| ports-implemented = <0x1>; |
| }; |
| |
| /* OCP2SCP1 */ |
| /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
| gpmc: gpmc@50000000 { |
| compatible = "ti,am3352-gpmc"; |
| ti,hwmods = "gpmc"; |
| reg = <0x50000000 0x37c>; /* device IO registers */ |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&edma_xbar 4 0>; |
| dma-names = "rxtx"; |
| gpmc,num-cs = <8>; |
| gpmc,num-waitpins = <2>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| target-module@56000000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x5600fe00 0x4>, |
| <0x5600fe10 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x56000000 0x2000000>; |
| }; |
| |
| crossbar_mpu: crossbar@4a002a48 { |
| compatible = "ti,irq-crossbar"; |
| reg = <0x4a002a48 0x130>; |
| interrupt-controller; |
| interrupt-parent = <&wakeupgen>; |
| #interrupt-cells = <3>; |
| ti,max-irqs = <160>; |
| ti,max-crossbar-sources = <MAX_SOURCES>; |
| ti,reg-size = <2>; |
| ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| ti,irqs-skip = <10 133 139 140>; |
| ti,irqs-safe-map = <0>; |
| }; |
| |
| target-module@58000000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x58000000 4>, |
| <0x58000014 4>; |
| reg-names = "rev", "syss"; |
| ti,syss-mask = <1>; |
| clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>, |
| <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, |
| <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>, |
| <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>; |
| clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x58000000 0x800000>; |
| |
| dss: dss@0 { |
| compatible = "ti,dra7-dss"; |
| /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ |
| /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ |
| status = "disabled"; |
| /* CTRL_CORE_DSS_PLL_CONTROL */ |
| syscon-pll-ctrl = <&scm_conf 0x538>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0x800000>; |
| |
| target-module@1000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x1000 0x4>, |
| <0x1010 0x4>, |
| <0x1014 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
| SYSC_OMAP2_ENAWAKEUP | |
| SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,syss-mask = <1>; |
| clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x1000 0x1000>; |
| |
| dispc@0 { |
| compatible = "ti,dra7-dispc"; |
| reg = <0 0x1000>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; |
| clock-names = "fck"; |
| /* CTRL_CORE_SMA_SW_1 */ |
| syscon-pol = <&scm_conf 0x534>; |
| }; |
| }; |
| |
| target-module@40000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x40000 0x4>, |
| <0x40010 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; |
| clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, |
| <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; |
| clock-names = "fck", "dss_clk"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x40000 0x40000>; |
| |
| hdmi: encoder@0 { |
| compatible = "ti,dra7-hdmi"; |
| reg = <0 0x200>, |
| <0x200 0x80>, |
| <0x300 0x80>, |
| <0x20000 0x19000>; |
| reg-names = "wp", "pll", "phy", "core"; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, |
| <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; |
| clock-names = "fck", "sys_clk"; |
| dmas = <&sdma_xbar 76>; |
| dma-names = "audio_tx"; |
| }; |
| }; |
| }; |
| }; |
| |
| aes1_target: target-module@4b500000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x4b500080 0x4>, |
| <0x4b500084 0x4>, |
| <0x4b500088 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4sec_clkdm */ |
| clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4b500000 0x1000>; |
| |
| aes1: aes@0 { |
| compatible = "ti,omap4-aes"; |
| reg = <0 0xa0>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; |
| dma-names = "tx", "rx"; |
| clocks = <&l3_iclk_div>; |
| clock-names = "fck"; |
| }; |
| }; |
| |
| aes2_target: target-module@4b700000 { |
| compatible = "ti,sysc-omap2", "ti,sysc"; |
| reg = <0x4b700080 0x4>, |
| <0x4b700084 0x4>, |
| <0x4b700088 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>, |
| <SYSC_IDLE_SMART_WKUP>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): per_pwrdm, l4sec_clkdm */ |
| clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4b700000 0x1000>; |
| |
| aes2: aes@0 { |
| compatible = "ti,omap4-aes"; |
| reg = <0 0xa0>; |
| interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; |
| dma-names = "tx", "rx"; |
| clocks = <&l3_iclk_div>; |
| clock-names = "fck"; |
| }; |
| }; |
| |
| sham_target: target-module@4b101000 { |
| compatible = "ti,sysc-omap3-sham", "ti,sysc"; |
| reg = <0x4b101100 0x4>, |
| <0x4b101110 0x4>, |
| <0x4b101114 0x4>; |
| reg-names = "rev", "sysc", "syss"; |
| ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| SYSC_OMAP2_AUTOIDLE)>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,syss-mask = <1>; |
| /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ |
| clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x4b101000 0x1000>; |
| |
| sham: sham@0 { |
| compatible = "ti,omap5-sham"; |
| reg = <0 0x300>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&edma_xbar 119 0>; |
| dma-names = "rx"; |
| clocks = <&l3_iclk_div>; |
| clock-names = "fck"; |
| }; |
| }; |
| |
| opp_supply_mpu: opp-supply@4a003b20 { |
| compatible = "ti,omap5-opp-supply"; |
| reg = <0x4a003b20 0xc>; |
| ti,efuse-settings = < |
| /* uV offset */ |
| 1060000 0x0 |
| 1160000 0x4 |
| 1210000 0x8 |
| >; |
| ti,absolute-max-voltage-uv = <1500000>; |
| }; |
| |
| }; |
| |
| thermal_zones: thermal-zones { |
| #include "omap4-cpu-thermal.dtsi" |
| #include "omap5-gpu-thermal.dtsi" |
| #include "omap5-core-thermal.dtsi" |
| #include "dra7-dspeve-thermal.dtsi" |
| #include "dra7-iva-thermal.dtsi" |
| }; |
| |
| }; |
| |
| &cpu_thermal { |
| polling-delay = <500>; /* milliseconds */ |
| coefficients = <0 2000>; |
| }; |
| |
| &gpu_thermal { |
| coefficients = <0 2000>; |
| }; |
| |
| &core_thermal { |
| coefficients = <0 2000>; |
| }; |
| |
| &dspeve_thermal { |
| coefficients = <0 2000>; |
| }; |
| |
| &iva_thermal { |
| coefficients = <0 2000>; |
| }; |
| |
| &cpu_crit { |
| temperature = <120000>; /* milli Celsius */ |
| }; |
| |
| &core_crit { |
| temperature = <120000>; /* milli Celsius */ |
| }; |
| |
| &gpu_crit { |
| temperature = <120000>; /* milli Celsius */ |
| }; |
| |
| &dspeve_crit { |
| temperature = <120000>; /* milli Celsius */ |
| }; |
| |
| &iva_crit { |
| temperature = <120000>; /* milli Celsius */ |
| }; |
| |
| #include "dra7-l4.dtsi" |
| #include "dra7xx-clocks.dtsi" |
| |
| &prm { |
| prm_dsp1: prm@400 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x400 0x100>; |
| #reset-cells = <1>; |
| }; |
| |
| prm_ipu: prm@500 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x500 0x100>; |
| #reset-cells = <1>; |
| }; |
| |
| prm_core: prm@700 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x700 0x100>; |
| #reset-cells = <1>; |
| }; |
| |
| prm_iva: prm@f00 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0xf00 0x100>; |
| }; |
| |
| prm_dsp2: prm@1b00 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x1b00 0x40>; |
| #reset-cells = <1>; |
| }; |
| |
| prm_eve1: prm@1b40 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x1b40 0x40>; |
| }; |
| |
| prm_eve2: prm@1b80 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x1b80 0x40>; |
| }; |
| |
| prm_eve3: prm@1bc0 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x1bc0 0x40>; |
| }; |
| |
| prm_eve4: prm@1c00 { |
| compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; |
| reg = <0x1c00 0x60>; |
| }; |
| }; |
| |
| /* Preferred always-on timer for clockevent */ |
| &timer1_target { |
| ti,no-reset-on-init; |
| ti,no-idle; |
| timer@0 { |
| assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; |
| assigned-clock-parents = <&sys_32k_ck>; |
| }; |
| }; |
| |
| /* Local timers, see ARM architected timer wrap erratum i940 */ |
| &timer3_target { |
| ti,no-reset-on-init; |
| ti,no-idle; |
| timer@0 { |
| assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; |
| assigned-clock-parents = <&timer_sys_clk_div>; |
| }; |
| }; |
| |
| &timer4_target { |
| ti,no-reset-on-init; |
| ti,no-idle; |
| timer@0 { |
| assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; |
| assigned-clock-parents = <&timer_sys_clk_div>; |
| }; |
| }; |
