| Freescale i.MX7 Mipi CSI2 |
| ========================= |
| |
| mipi_csi2 node |
| -------------- |
| |
| This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is |
| compatible with previous version of Samsung D-phy. |
| |
| Required properties: |
| |
| - compatible : "fsl,imx7-mipi-csi2"; |
| - reg : base address and length of the register set for the device; |
| - interrupts : should contain MIPI CSIS interrupt; |
| - clocks : list of clock specifiers, see |
| Documentation/devicetree/bindings/clock/clock-bindings.txt for details; |
| - clock-names : must contain "pclk", "wrap" and "phy" entries, matching |
| entries in the clock property; |
| - power-domains : a phandle to the power domain, see |
| Documentation/devicetree/bindings/power/power_domain.txt for details. |
| - reset-names : should include following entry "mrst"; |
| - resets : a list of phandle, should contain reset entry of |
| reset-names; |
| - phy-supply : from the generic phy bindings, a phandle to a regulator that |
| provides power to MIPI CSIS core; |
| |
| Optional properties: |
| |
| - clock-frequency : The IP's main (system bus) clock frequency in Hz, default |
| value when this property is not specified is 166 MHz; |
| - fsl,csis-hs-settle : differential receiver (HS-RX) settle time; |
| |
| The device node should contain two 'port' child nodes with one child 'endpoint' |
| node, according to the bindings defined in: |
| Documentation/devicetree/bindings/ media/video-interfaces.txt. |
| The following are properties specific to those nodes. |
| |
| port node |
| --------- |
| |
| - reg : (required) can take the values 0 or 1, where 0 shall be |
| related to the sink port and port 1 shall be the source |
| one; |
| |
| endpoint node |
| ------------- |
| |
| - data-lanes : (required) an array specifying active physical MIPI-CSI2 |
| data input lanes and their mapping to logical lanes; this |
| shall only be applied to port 0 (sink port), the array's |
| content is unused only its length is meaningful, |
| in this case the maximum length supported is 2; |
| |
| example: |
| |
| mipi_csi: mipi-csi@30750000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible = "fsl,imx7-mipi-csi2"; |
| reg = <0x30750000 0x10000>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX7D_IPG_ROOT_CLK>, |
| <&clks IMX7D_MIPI_CSI_ROOT_CLK>, |
| <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; |
| clock-names = "pclk", "wrap", "phy"; |
| clock-frequency = <166000000>; |
| power-domains = <&pgc_mipi_phy>; |
| phy-supply = <®_1p0d>; |
| resets = <&src IMX7_RESET_MIPI_PHY_MRST>; |
| reset-names = "mrst"; |
| fsl,csis-hs-settle = <3>; |
| |
| port@0 { |
| reg = <0>; |
| |
| mipi_from_sensor: endpoint { |
| remote-endpoint = <&ov2680_to_mipi>; |
| data-lanes = <1>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| mipi_vc0_to_csi_mux: endpoint { |
| remote-endpoint = <&csi_mux_from_mipi_vc0>; |
| }; |
| }; |
| }; |