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The following bindings apply to a family of Display Processors sold as
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
DP650 processors that offer multiple composition layers, support for
rotation and scaling output.
Required properties:
- compatible: should be one of
depending on the particular implementation present in the hardware
- reg: Physical base address and size of the block of registers used by
the processor.
- interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
interrupt client nodes.
- interrupt-names: name of the engine inside the processor that will
use the corresponding interrupt. Should be one of "DE" or "SE".
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "pclk": for the APB interface clock
- "aclk": for the AXI interface clock
- "mclk": for the main processor clock
- "pxlclk": for the pixel clock feeding the output PLL of the processor.
- arm,malidp-output-port-lines: Array of u8 values describing the number
of output lines per channel (R, G and B).
Required sub-nodes:
- port: The Mali DP connection to an encoder input port. The connection
is modelled using the OF graph bindings specified in
Optional properties:
- memory-region: phandle to a node describing memory (see
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
- arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
levels of DP500's QoS signaling.
/ {
dp0: malidp@6f200000 {
compatible = "arm,mali-dp650";
reg = <0 0x6f200000 0 0x20000>;
memory-region = <&display_reserved>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
interrupt-names = "DE", "SE";
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-high-level = <0xd000d000>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;