blob: a3c1dffaa4bb4a0a5722cef5cd23bab4ecdf278d [file] [log] [blame]
* Socionext NetSec Ethernet Controller IP
Required properties:
- compatible: Should be "socionext,synquacer-netsec"
- reg: Address and length of the control register area, followed by the
address and length of the EEPROM holding the MAC address and
microengine firmware
- interrupts: Should contain ethernet controller interrupt
- clocks: phandle to the PHY reference clock
- clock-names: Should be "phy_ref_clk"
- phy-mode: See ethernet.txt file in the same directory
- phy-handle: See ethernet.txt in the same directory.
- mdio device tree subnode: When the Netsec has a phy connected to its local
mdio, there must be device tree subnode with the following
required properties:
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.
For each phy on the mdio bus, there must be a node with the following
- compatible: Refer to phy.txt
- reg: phy id used to communicate to phy.
Optional properties: (See ethernet.txt file in the same directory)
- dma-coherent: Boolean property, must only be present if memory
accesses performed by the device are cache coherent.
- max-speed: See ethernet.txt in the same directory.
- max-frame-size: See ethernet.txt in the same directory.
The MAC address will be determined using the optional properties
defined in ethernet.txt. The 'phy-mode' property is required, but may
be set to the empty string if the PHY configuration is programmed by
the firmware or set by hardware straps, and needs to be preserved.
eth0: ethernet@522d0000 {
compatible = "socionext,synquacer-netsec";
reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_netsec>;
clock-names = "phy_ref_clk";
phy-mode = "rgmii";
max-speed = <1000>;
max-frame-size = <9000>;
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;