| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2024 Linumiz |
| * Author: Parthiban <parthiban@linumiz.com> |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| model = "Seeed NPi-iMX6ULL Dev Board"; |
| compatible = "seeed,imx6ull-seeed-npi", "fsl,imx6ull"; |
| |
| reg_dcdc_3v3: regulator-dcdc-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "DCDC_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| reg_dram_1v35: regulator-dram-1v35 { |
| compatible = "regulator-fixed"; |
| regulator-name = "DRAM_1V35"; |
| regulator-min-microvolt = <1350000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-always-on; |
| vin-supply = <®_dcdc_3v3>; |
| }; |
| |
| reg_vdd_arm_soc_in: regulator-vdd-arm-soc-in { |
| compatible = "regulator-fixed"; |
| regulator-name = "VDD_ARM_SOC_IN"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-always-on; |
| vin-supply = <®_dcdc_3v3>; |
| }; |
| |
| reg_dcdc_1v8: regulator-dcdc-1v8 { |
| compatible = "regulator-fixed"; |
| regulator-name = "DCDC_1V8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| vin-supply = <®_dcdc_3v3>; |
| }; |
| |
| reg_sd1_vqmmc: regulator-sd1-vqmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "NVCC_SD"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_vqmmc>; |
| regulator-always-on; |
| vin-supply = <®_dcdc_1v8>; |
| }; |
| }; |
| |
| &gpmi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpmi_nand>; |
| status = "disabled"; |
| }; |
| |
| &usdhc1 { |
| vqmmc-supply = <®_sd1_vqmmc>; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| keep-power-in-suspend; |
| status = "disabled"; |
| }; |
| |
| &iomuxc { |
| pinctrl_gpmi_nand: gpminandgrp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 |
| MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 |
| MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 |
| MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 |
| MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 |
| MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 |
| MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 |
| MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 |
| MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 |
| MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 |
| MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 |
| MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 |
| MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 |
| MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 |
| MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 |
| MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 |
| MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 |
| >; |
| }; |
| |
| pinctrl_reg_vqmmc: usdhc1regvqmmc { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 |
| MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 |
| MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 |
| MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 |
| MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 |
| >; |
| }; |
| }; |
