arch/arm64/boot/dts/realtek/rtd16xx.dtsi

// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
 * Realtek RTD16xx SoC family
 *
 * Copyright (c) 2019 Realtek Semiconductor Corp.
 * Copyright (c) 2019 Andreas Färber
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		rpc_comm: rpc@2f000 {
			reg = <0x2f000 0x1000>;
		};

		rpc_ringbuf: rpc@1ffe000 {
			reg = <0x1ffe000 0x4000>;
		};

		tee: tee@10100000 {
			reg = <0x10100000 0xf00000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&l3>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x200>;
			enable-method = "psci";
			next-level-cache = <&l3>;
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x300>;
			enable-method = "psci";
			next-level-cache = <&l3>;
		};

		cpu4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x400>;
			enable-method = "psci";
			next-level-cache = <&l3>;
		};

		cpu5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x500>;
			enable-method = "psci";
			next-level-cache = <&l3>;
		};

		l2: l2-cache {
			compatible = "cache";
			next-level-cache = <&l3>;
			cache-level = <2>;
			cache-unified;

		};

		l3: l3-cache {
			compatible = "cache";
			cache-level = <3>;
			cache-unified;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	arm_pmu: pmu {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
			<&cpu3>, <&cpu4>, <&cpu5>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	osc27M: osc {
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
		clock-output-names = "osc27M";
		#clock-cells = <0>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
			 <0x98000000 0x98000000 0x68000000>;

		rbus: bus@98000000 {
			compatible = "simple-bus";
			reg = <0x98000000 0x200000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x98000000 0x200000>;

			crt: syscon@0 {
				compatible = "syscon", "simple-mfd";
				reg = <0x0 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x0 0x1000>;
			};

			iso: syscon@7000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x7000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x7000 0x1000>;
			};

			sb2: syscon@1a000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1a000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1a000 0x1000>;
			};

			misc: syscon@1b000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1b000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1b000 0x1000>;
			};

			scpu_wrapper: syscon@1d000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1d000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1d000 0x1000>;
			};
		};

		gic: interrupt-controller@ff100000 {
			compatible = "arm,gic-v3";
			reg = <0xff100000 0x10000>,
			      <0xff140000 0xc0000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};

&iso {
	uart0: serial@800 {
		compatible = "snps,dw-apb-uart";
		reg = <0x800 0x400>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <27000000>;
		status = "disabled";
	};
};

&misc {
	uart1: serial@200 {
		compatible = "snps,dw-apb-uart";
		reg = <0x200 0x400>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <432000000>;
		status = "disabled";
	};

	uart2: serial@400 {
		compatible = "snps,dw-apb-uart";
		reg = <0x400 0x400>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <432000000>;
		status = "disabled";
	};
};