arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
 */

/dts-v1/;
#include "jh7110-common.dtsi"

/ {
	model = "Pine64 Star64";
	compatible = "pine64,star64", "starfive,jh7110";
	aliases {
		ethernet1 = &gmac1;
	};
};

&gmac0 {
	starfive,tx-use-rgmii-clk;
	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
};

&gmac1 {
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	starfive,tx-use-rgmii-clk;
	assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
	assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		phy1: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

&pcie1 {
	status = "okay";
};

&phy0 {
	rx-internal-delay-ps = <1500>;
	motorcomm,rx-clk-drv-microamp = <2910>;
	motorcomm,rx-data-drv-microamp = <2910>;
	motorcomm,tx-clk-adj-enabled;
	motorcomm,tx-clk-10-inverted;
	motorcomm,tx-clk-100-inverted;
	motorcomm,tx-clk-1000-inverted;
};

&phy1 {
	rx-internal-delay-ps = <0>;
	tx-internal-delay-ps = <300>;
	motorcomm,rx-clk-drv-microamp = <2910>;
	motorcomm,rx-data-drv-microamp = <2910>;
	motorcomm,tx-clk-adj-enabled;
	motorcomm,tx-clk-10-inverted;
	motorcomm,tx-clk-100-inverted;
};