| Mediatek infracfg controller |
| ============================ |
| |
| The Mediatek infracfg controller provides various clocks and reset |
| outputs to the system. |
| |
| Required Properties: |
| |
| - compatible: Should be one of: |
| - "mediatek,mt2701-infracfg", "syscon" |
| - "mediatek,mt2712-infracfg", "syscon" |
| - "mediatek,mt6779-infracfg_ao", "syscon" |
| - "mediatek,mt6797-infracfg", "syscon" |
| - "mediatek,mt7622-infracfg", "syscon" |
| - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" |
| - "mediatek,mt7629-infracfg", "syscon" |
| - "mediatek,mt8135-infracfg", "syscon" |
| - "mediatek,mt8173-infracfg", "syscon" |
| - "mediatek,mt8183-infracfg", "syscon" |
| - "mediatek,mt8516-infracfg", "syscon" |
| - #clock-cells: Must be 1 |
| - #reset-cells: Must be 1 |
| |
| The infracfg controller uses the common clk binding from |
| Documentation/devicetree/bindings/clock/clock-bindings.txt |
| The available clocks are defined in dt-bindings/clock/mt*-clk.h. |
| Also it uses the common reset controller binding from |
| Documentation/devicetree/bindings/reset/reset.txt. |
| The available reset outputs are defined in |
| dt-bindings/reset/mt*-resets.h |
| |
| Example: |
| |
| infracfg: power-controller@10001000 { |
| compatible = "mediatek,mt8173-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
