arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts

// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2019, Intel Corporation
 */
#include "socfpga_agilex.dtsi"

/ {
	model = "SoCFPGA Agilex SoCDK";

	aliases {
		serial0 = &uart0;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};
};

&gpio1 {
	status = "okay";
};

&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <4>;

			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			txen-skew-ps = <0>; /* -420ps */
			txc-skew-ps = <900>; /* 0ps */
			rxdv-skew-ps = <420>; /* 0ps */
			rxc-skew-ps = <1680>; /* 780ps */
		};
	};
};

&mmc {
	status = "okay";
	cap-sd-highspeed;
	broken-cd;
	bus-width = <4>;
};

&uart0 {
	status = "okay";
};

&watchdog0 {
	status = "okay";
};