| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (c) 2018 MediaTek Inc. |
| * Author: Ben Ho <ben.ho@mediatek.com> |
| * Erin Lo <erin.lo@mediatek.com> |
| */ |
| |
| #include <dt-bindings/clock/mt8183-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include "mt8183-pinfunc.h" |
| |
| / { |
| compatible = "mediatek,mt8183"; |
| interrupt-parent = <&sysirq>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| i2c7 = &i2c7; |
| i2c8 = &i2c8; |
| i2c9 = &i2c9; |
| i2c10 = &i2c10; |
| i2c11 = &i2c11; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x000>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <741>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x001>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <741>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x002>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <741>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x003>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <741>; |
| }; |
| |
| cpu4: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu5: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73"; |
| reg = <0x101>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu6: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73"; |
| reg = <0x102>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| }; |
| |
| cpu7: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73"; |
| reg = <0x103>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| }; |
| }; |
| |
| pmu-a53 { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; |
| }; |
| |
| pmu-a73 { |
| compatible = "arm,cortex-a73-pmu"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| clk26m: oscillator { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| clock-output-names = "clk26m"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| soc_data: soc_data@8000000 { |
| compatible = "mediatek,mt8183-efuse", |
| "mediatek,efuse"; |
| reg = <0 0x08000000 0 0x0010>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <4>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| <0 0x0c100000 0 0x200000>, /* GICR */ |
| <0 0x0c400000 0 0x2000>, /* GICC */ |
| <0 0x0c410000 0 0x1000>, /* GICH */ |
| <0 0x0c420000 0 0x2000>; /* GICV */ |
| |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; |
| ppi-partitions { |
| ppi_cluster0: interrupt-partition-0 { |
| affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; |
| }; |
| ppi_cluster1: interrupt-partition-1 { |
| affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; |
| }; |
| }; |
| }; |
| |
| mcucfg: syscon@c530000 { |
| compatible = "mediatek,mt8183-mcucfg", "syscon"; |
| reg = <0 0x0c530000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| sysirq: interrupt-controller@c530a80 { |
| compatible = "mediatek,mt8183-sysirq", |
| "mediatek,mt6577-sysirq"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| reg = <0 0x0c530a80 0 0x50>; |
| }; |
| |
| topckgen: syscon@10000000 { |
| compatible = "mediatek,mt8183-topckgen", "syscon"; |
| reg = <0 0x10000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: syscon@10001000 { |
| compatible = "mediatek,mt8183-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pio: pinctrl@10005000 { |
| compatible = "mediatek,mt8183-pinctrl"; |
| reg = <0 0x10005000 0 0x1000>, |
| <0 0x11f20000 0 0x1000>, |
| <0 0x11e80000 0 0x1000>, |
| <0 0x11e70000 0 0x1000>, |
| <0 0x11e90000 0 0x1000>, |
| <0 0x11d30000 0 0x1000>, |
| <0 0x11d20000 0 0x1000>, |
| <0 0x11c50000 0 0x1000>, |
| <0 0x11f30000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "iocfg0", "iocfg1", "iocfg2", |
| "iocfg3", "iocfg4", "iocfg5", |
| "iocfg6", "iocfg7", "iocfg8", |
| "eint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 192>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <2>; |
| }; |
| |
| apmixedsys: syscon@1000c000 { |
| compatible = "mediatek,mt8183-apmixedsys", "syscon"; |
| reg = <0 0x1000c000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pwrap: pwrap@1000d000 { |
| compatible = "mediatek,mt8183-pwrap"; |
| reg = <0 0x1000d000 0 0x1000>; |
| reg-names = "pwrap"; |
| interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, |
| <&infracfg CLK_INFRA_PMIC_AP>; |
| clock-names = "spi", "wrap"; |
| }; |
| |
| auxadc: auxadc@11001000 { |
| compatible = "mediatek,mt8183-auxadc", |
| "mediatek,mt8173-auxadc"; |
| reg = <0 0x11001000 0 0x1000>; |
| clocks = <&infracfg CLK_INFRA_AUXADC>; |
| clock-names = "main"; |
| #io-channel-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt8183-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x1000>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt8183-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x1000>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt8183-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x1000>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@11005000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11005000 0 0x1000>, |
| <0 0x11000600 0 0x80>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C6>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11007000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11007000 0 0x1000>, |
| <0 0x11000080 0 0x80>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C0>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@11008000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11008000 0 0x1000>, |
| <0 0x11000100 0 0x80>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C1>, |
| <&infracfg CLK_INFRA_AP_DMA>, |
| <&infracfg CLK_INFRA_I2C1_ARBITER>; |
| clock-names = "main", "dma","arb"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@11009000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11009000 0 0x1000>, |
| <0 0x11000280 0 0x80>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C2>, |
| <&infracfg CLK_INFRA_AP_DMA>, |
| <&infracfg CLK_INFRA_I2C2_ARBITER>; |
| clock-names = "main", "dma", "arb"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@1100a000 { |
| compatible = "mediatek,mt8183-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x1100a000 0 0x1000>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, |
| <&topckgen CLK_TOP_MUX_SPI>, |
| <&infracfg CLK_INFRA_SPI0>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@1100f000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x1100f000 0 0x1000>, |
| <0 0x11000400 0 0x80>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C3>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@11010000 { |
| compatible = "mediatek,mt8183-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11010000 0 0x1000>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, |
| <&topckgen CLK_TOP_MUX_SPI>, |
| <&infracfg CLK_INFRA_SPI1>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@11011000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11011000 0 0x1000>, |
| <0 0x11000480 0 0x80>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C4>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@11012000 { |
| compatible = "mediatek,mt8183-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11012000 0 0x1000>; |
| interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, |
| <&topckgen CLK_TOP_MUX_SPI>, |
| <&infracfg CLK_INFRA_SPI2>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@11013000 { |
| compatible = "mediatek,mt8183-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11013000 0 0x1000>; |
| interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, |
| <&topckgen CLK_TOP_MUX_SPI>, |
| <&infracfg CLK_INFRA_SPI3>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@11014000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11014000 0 0x1000>, |
| <0 0x11000180 0 0x80>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C1_IMM>, |
| <&infracfg CLK_INFRA_AP_DMA>, |
| <&infracfg CLK_INFRA_I2C1_ARBITER>; |
| clock-names = "main", "dma", "arb"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@11015000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11015000 0 0x1000>, |
| <0 0x11000300 0 0x80>; |
| interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C2_IMM>, |
| <&infracfg CLK_INFRA_AP_DMA>, |
| <&infracfg CLK_INFRA_I2C2_ARBITER>; |
| clock-names = "main", "dma", "arb"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@11016000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11016000 0 0x1000>, |
| <0 0x11000500 0 0x80>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C5>, |
| <&infracfg CLK_INFRA_AP_DMA>, |
| <&infracfg CLK_INFRA_I2C5_ARBITER>; |
| clock-names = "main", "dma", "arb"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@11017000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x11017000 0 0x1000>, |
| <0 0x11000580 0 0x80>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C5_IMM>, |
| <&infracfg CLK_INFRA_AP_DMA>, |
| <&infracfg CLK_INFRA_I2C5_ARBITER>; |
| clock-names = "main", "dma", "arb"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@11018000 { |
| compatible = "mediatek,mt8183-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11018000 0 0x1000>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, |
| <&topckgen CLK_TOP_MUX_SPI>, |
| <&infracfg CLK_INFRA_SPI4>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@11019000 { |
| compatible = "mediatek,mt8183-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0 0x11019000 0 0x1000>; |
| interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, |
| <&topckgen CLK_TOP_MUX_SPI>, |
| <&infracfg CLK_INFRA_SPI5>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@1101a000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x1101a000 0 0x1000>, |
| <0 0x11000680 0 0x80>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C7>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c8: i2c@1101b000 { |
| compatible = "mediatek,mt8183-i2c"; |
| reg = <0 0x1101b000 0 0x1000>, |
| <0 0x11000700 0 0x80>; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; |
| clocks = <&infracfg CLK_INFRA_I2C8>, |
| <&infracfg CLK_INFRA_AP_DMA>; |
| clock-names = "main", "dma"; |
| clock-div = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| audiosys: syscon@11220000 { |
| compatible = "mediatek,mt8183-audiosys", "syscon"; |
| reg = <0 0x11220000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| efuse: efuse@11f10000 { |
| compatible = "mediatek,mt8183-efuse", |
| "mediatek,efuse"; |
| reg = <0 0x11f10000 0 0x1000>; |
| }; |
| |
| mfgcfg: syscon@13000000 { |
| compatible = "mediatek,mt8183-mfgcfg", "syscon"; |
| reg = <0 0x13000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| mmsys: syscon@14000000 { |
| compatible = "mediatek,mt8183-mmsys", "syscon"; |
| reg = <0 0x14000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| imgsys: syscon@15020000 { |
| compatible = "mediatek,mt8183-imgsys", "syscon"; |
| reg = <0 0x15020000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| vdecsys: syscon@16000000 { |
| compatible = "mediatek,mt8183-vdecsys", "syscon"; |
| reg = <0 0x16000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| vencsys: syscon@17000000 { |
| compatible = "mediatek,mt8183-vencsys", "syscon"; |
| reg = <0 0x17000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ipu_conn: syscon@19000000 { |
| compatible = "mediatek,mt8183-ipu_conn", "syscon"; |
| reg = <0 0x19000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ipu_adl: syscon@19010000 { |
| compatible = "mediatek,mt8183-ipu_adl", "syscon"; |
| reg = <0 0x19010000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ipu_core0: syscon@19180000 { |
| compatible = "mediatek,mt8183-ipu_core0", "syscon"; |
| reg = <0 0x19180000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| ipu_core1: syscon@19280000 { |
| compatible = "mediatek,mt8183-ipu_core1", "syscon"; |
| reg = <0 0x19280000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| camsys: syscon@1a000000 { |
| compatible = "mediatek,mt8183-camsys", "syscon"; |
| reg = <0 0x1a000000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| }; |
