| // SPDX-License-Identifier: GPL-2.0 |
| |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/input/gpio-keys.h> |
| #include <dt-bindings/mfd/max77620.h> |
| #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
| #include "tegra210.dtsi" |
| |
| / { |
| aliases { |
| serial0 = &uarta; |
| }; |
| |
| chosen { |
| bootargs = "earlycon"; |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0x0 0xc0000000>; |
| }; |
| |
| pinmux: pinmux@700008d4 { |
| status = "okay"; |
| pinctrl-names = "boot"; |
| pinctrl-0 = <&state_boot>; |
| |
| state_boot: pinmux { |
| pex_l0_rst_n_pa0 { |
| nvidia,pins = "pex_l0_rst_n_pa0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| pex_l0_clkreq_n_pa1 { |
| nvidia,pins = "pex_l0_clkreq_n_pa1"; |
| nvidia,function = "pe0"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| pex_wake_n_pa2 { |
| nvidia,pins = "pex_wake_n_pa2"; |
| nvidia,function = "pe"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| pex_l1_rst_n_pa3 { |
| nvidia,pins = "pex_l1_rst_n_pa3"; |
| nvidia,function = "pe1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| pex_l1_clkreq_n_pa4 { |
| nvidia,pins = "pex_l1_clkreq_n_pa4"; |
| nvidia,function = "pe1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| sata_led_active_pa5 { |
| nvidia,pins = "sata_led_active_pa5"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pa6 { |
| nvidia,pins = "pa6"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap1_fs_pb0 { |
| nvidia,pins = "dap1_fs_pb0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap1_din_pb1 { |
| nvidia,pins = "dap1_din_pb1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap1_dout_pb2 { |
| nvidia,pins = "dap1_dout_pb2"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap1_sclk_pb3 { |
| nvidia,pins = "dap1_sclk_pb3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi2_mosi_pb4 { |
| nvidia,pins = "spi2_mosi_pb4"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi2_miso_pb5 { |
| nvidia,pins = "spi2_miso_pb5"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi2_sck_pb6 { |
| nvidia,pins = "spi2_sck_pb6"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi2_cs0_pb7 { |
| nvidia,pins = "spi2_cs0_pb7"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi1_mosi_pc0 { |
| nvidia,pins = "spi1_mosi_pc0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi1_miso_pc1 { |
| nvidia,pins = "spi1_miso_pc1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi1_sck_pc2 { |
| nvidia,pins = "spi1_sck_pc2"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi1_cs0_pc3 { |
| nvidia,pins = "spi1_cs0_pc3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi1_cs1_pc4 { |
| nvidia,pins = "spi1_cs1_pc4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi4_sck_pc5 { |
| nvidia,pins = "spi4_sck_pc5"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi4_cs0_pc6 { |
| nvidia,pins = "spi4_cs0_pc6"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi4_mosi_pc7 { |
| nvidia,pins = "spi4_mosi_pc7"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spi4_miso_pd0 { |
| nvidia,pins = "spi4_miso_pd0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_tx_pd1 { |
| nvidia,pins = "uart3_tx_pd1"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_rx_pd2 { |
| nvidia,pins = "uart3_rx_pd2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_rts_pd3 { |
| nvidia,pins = "uart3_rts_pd3"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_cts_pd4 { |
| nvidia,pins = "uart3_cts_pd4"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dmic1_clk_pe0 { |
| nvidia,pins = "dmic1_clk_pe0"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dmic1_dat_pe1 { |
| nvidia,pins = "dmic1_dat_pe1"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dmic2_clk_pe2 { |
| nvidia,pins = "dmic2_clk_pe2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dmic2_dat_pe3 { |
| nvidia,pins = "dmic2_dat_pe3"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dmic3_clk_pe4 { |
| nvidia,pins = "dmic3_clk_pe4"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dmic3_dat_pe5 { |
| nvidia,pins = "dmic3_dat_pe5"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pe6 { |
| nvidia,pins = "pe6"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pe7 { |
| nvidia,pins = "pe7"; |
| nvidia,function = "pwm3"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| gen3_i2c_scl_pf0 { |
| nvidia,pins = "gen3_i2c_scl_pf0"; |
| nvidia,function = "i2c3"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| gen3_i2c_sda_pf1 { |
| nvidia,pins = "gen3_i2c_sda_pf1"; |
| nvidia,function = "i2c3"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_tx_pg0 { |
| nvidia,pins = "uart2_tx_pg0"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_rx_pg1 { |
| nvidia,pins = "uart2_rx_pg1"; |
| nvidia,function = "uartb"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_rts_pg2 { |
| nvidia,pins = "uart2_rts_pg2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_cts_pg3 { |
| nvidia,pins = "uart2_cts_pg3"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| wifi_en_ph0 { |
| nvidia,pins = "wifi_en_ph0"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| wifi_rst_ph1 { |
| nvidia,pins = "wifi_rst_ph1"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| wifi_wake_ap_ph2 { |
| nvidia,pins = "wifi_wake_ap_ph2"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| ap_wake_bt_ph3 { |
| nvidia,pins = "ap_wake_bt_ph3"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| bt_rst_ph4 { |
| nvidia,pins = "bt_rst_ph4"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| bt_wake_ap_ph5 { |
| nvidia,pins = "bt_wake_ap_ph5"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| ph6 { |
| nvidia,pins = "ph6"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| ap_wake_nfc_ph7 { |
| nvidia,pins = "ap_wake_nfc_ph7"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| nfc_en_pi0 { |
| nvidia,pins = "nfc_en_pi0"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| nfc_int_pi1 { |
| nvidia,pins = "nfc_int_pi1"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| gps_en_pi2 { |
| nvidia,pins = "gps_en_pi2"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| gps_rst_pi3 { |
| nvidia,pins = "gps_rst_pi3"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart4_tx_pi4 { |
| nvidia,pins = "uart4_tx_pi4"; |
| nvidia,function = "uartd"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart4_rx_pi5 { |
| nvidia,pins = "uart4_rx_pi5"; |
| nvidia,function = "uartd"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart4_rts_pi6 { |
| nvidia,pins = "uart4_rts_pi6"; |
| nvidia,function = "uartd"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart4_cts_pi7 { |
| nvidia,pins = "uart4_cts_pi7"; |
| nvidia,function = "uartd"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| gen1_i2c_sda_pj0 { |
| nvidia,pins = "gen1_i2c_sda_pj0"; |
| nvidia,function = "i2c1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| gen1_i2c_scl_pj1 { |
| nvidia,pins = "gen1_i2c_scl_pj1"; |
| nvidia,function = "i2c1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| gen2_i2c_scl_pj2 { |
| nvidia,pins = "gen2_i2c_scl_pj2"; |
| nvidia,function = "i2c2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| gen2_i2c_sda_pj3 { |
| nvidia,pins = "gen2_i2c_sda_pj3"; |
| nvidia,function = "i2c2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| dap4_fs_pj4 { |
| nvidia,pins = "dap4_fs_pj4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap4_din_pj5 { |
| nvidia,pins = "dap4_din_pj5"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap4_dout_pj6 { |
| nvidia,pins = "dap4_dout_pj6"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap4_sclk_pj7 { |
| nvidia,pins = "dap4_sclk_pj7"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk0 { |
| nvidia,pins = "pk0"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk1 { |
| nvidia,pins = "pk1"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk2 { |
| nvidia,pins = "pk2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk3 { |
| nvidia,pins = "pk3"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk4 { |
| nvidia,pins = "pk4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk5 { |
| nvidia,pins = "pk5"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk6 { |
| nvidia,pins = "pk6"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pk7 { |
| nvidia,pins = "pk7"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pl0 { |
| nvidia,pins = "pl0"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pl1 { |
| nvidia,pins = "pl1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_clk_pm0 { |
| nvidia,pins = "sdmmc1_clk_pm0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_cmd_pm1 { |
| nvidia,pins = "sdmmc1_cmd_pm1"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_dat3_pm2 { |
| nvidia,pins = "sdmmc1_dat3_pm2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_dat2_pm3 { |
| nvidia,pins = "sdmmc1_dat2_pm3"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_dat1_pm4 { |
| nvidia,pins = "sdmmc1_dat1_pm4"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_dat0_pm5 { |
| nvidia,pins = "sdmmc1_dat0_pm5"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_clk_pp0 { |
| nvidia,pins = "sdmmc3_clk_pp0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_cmd_pp1 { |
| nvidia,pins = "sdmmc3_cmd_pp1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_dat3_pp2 { |
| nvidia,pins = "sdmmc3_dat3_pp2"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_dat2_pp3 { |
| nvidia,pins = "sdmmc3_dat2_pp3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_dat1_pp4 { |
| nvidia,pins = "sdmmc3_dat1_pp4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_dat0_pp5 { |
| nvidia,pins = "sdmmc3_dat0_pp5"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam1_mclk_ps0 { |
| nvidia,pins = "cam1_mclk_ps0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam2_mclk_ps1 { |
| nvidia,pins = "cam2_mclk_ps1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_i2c_scl_ps2 { |
| nvidia,pins = "cam_i2c_scl_ps2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_i2c_sda_ps3 { |
| nvidia,pins = "cam_i2c_sda_ps3"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_rst_ps4 { |
| nvidia,pins = "cam_rst_ps4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_af_en_ps5 { |
| nvidia,pins = "cam_af_en_ps5"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_flash_en_ps6 { |
| nvidia,pins = "cam_flash_en_ps6"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam1_pwdn_ps7 { |
| nvidia,pins = "cam1_pwdn_ps7"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam2_pwdn_pt0 { |
| nvidia,pins = "cam2_pwdn_pt0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cam1_strobe_pt1 { |
| nvidia,pins = "cam1_strobe_pt1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart1_tx_pu0 { |
| nvidia,pins = "uart1_tx_pu0"; |
| nvidia,function = "uarta"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart1_rx_pu1 { |
| nvidia,pins = "uart1_rx_pu1"; |
| nvidia,function = "uarta"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart1_rts_pu2 { |
| nvidia,pins = "uart1_rts_pu2"; |
| nvidia,function = "uarta"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| uart1_cts_pu3 { |
| nvidia,pins = "uart1_cts_pu3"; |
| nvidia,function = "uarta"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| lcd_bl_pwm_pv0 { |
| nvidia,pins = "lcd_bl_pwm_pv0"; |
| nvidia,function = "pwm0"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| lcd_bl_en_pv1 { |
| nvidia,pins = "lcd_bl_en_pv1"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| lcd_rst_pv2 { |
| nvidia,pins = "lcd_rst_pv2"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| lcd_gpio1_pv3 { |
| nvidia,pins = "lcd_gpio1_pv3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| lcd_gpio2_pv4 { |
| nvidia,pins = "lcd_gpio2_pv4"; |
| nvidia,function = "pwm1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| ap_ready_pv5 { |
| nvidia,pins = "ap_ready_pv5"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| touch_rst_pv6 { |
| nvidia,pins = "touch_rst_pv6"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| touch_clk_pv7 { |
| nvidia,pins = "touch_clk_pv7"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| modem_wake_ap_px0 { |
| nvidia,pins = "modem_wake_ap_px0"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| touch_int_px1 { |
| nvidia,pins = "touch_int_px1"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| motion_int_px2 { |
| nvidia,pins = "motion_int_px2"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| als_prox_int_px3 { |
| nvidia,pins = "als_prox_int_px3"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| temp_alert_px4 { |
| nvidia,pins = "temp_alert_px4"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| button_power_on_px5 { |
| nvidia,pins = "button_power_on_px5"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| button_vol_up_px6 { |
| nvidia,pins = "button_vol_up_px6"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| button_vol_down_px7 { |
| nvidia,pins = "button_vol_down_px7"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| button_slide_sw_py0 { |
| nvidia,pins = "button_slide_sw_py0"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| button_home_py1 { |
| nvidia,pins = "button_home_py1"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| lcd_te_py2 { |
| nvidia,pins = "lcd_te_py2"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_i2c_scl_py3 { |
| nvidia,pins = "pwr_i2c_scl_py3"; |
| nvidia,function = "i2cpmu"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_i2c_sda_py4 { |
| nvidia,pins = "pwr_i2c_sda_py4"; |
| nvidia,function = "i2cpmu"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| clk_32k_out_py5 { |
| nvidia,pins = "clk_32k_out_py5"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pz0 { |
| nvidia,pins = "pz0"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pz1 { |
| nvidia,pins = "pz1"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pz2 { |
| nvidia,pins = "pz2"; |
| nvidia,function = "rsvd2"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pz3 { |
| nvidia,pins = "pz3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pz4 { |
| nvidia,pins = "pz4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pz5 { |
| nvidia,pins = "pz5"; |
| nvidia,function = "soc"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap2_fs_paa0 { |
| nvidia,pins = "dap2_fs_paa0"; |
| nvidia,function = "i2s2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap2_sclk_paa1 { |
| nvidia,pins = "dap2_sclk_paa1"; |
| nvidia,function = "i2s2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap2_din_paa2 { |
| nvidia,pins = "dap2_din_paa2"; |
| nvidia,function = "i2s2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dap2_dout_paa3 { |
| nvidia,pins = "dap2_dout_paa3"; |
| nvidia,function = "i2s2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| aud_mclk_pbb0 { |
| nvidia,pins = "aud_mclk_pbb0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dvfs_pwm_pbb1 { |
| nvidia,pins = "dvfs_pwm_pbb1"; |
| nvidia,function = "cldvfs"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| dvfs_clk_pbb2 { |
| nvidia,pins = "dvfs_clk_pbb2"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| gpio_x1_aud_pbb3 { |
| nvidia,pins = "gpio_x1_aud_pbb3"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| gpio_x3_aud_pbb4 { |
| nvidia,pins = "gpio_x3_aud_pbb4"; |
| nvidia,function = "rsvd0"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| hdmi_cec_pcc0 { |
| nvidia,pins = "hdmi_cec_pcc0"; |
| nvidia,function = "cec"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| hdmi_int_dp_hpd_pcc1 { |
| nvidia,pins = "hdmi_int_dp_hpd_pcc1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| spdif_out_pcc2 { |
| nvidia,pins = "spdif_out_pcc2"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| spdif_in_pcc3 { |
| nvidia,pins = "spdif_in_pcc3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| usb_vbus_en0_pcc4 { |
| nvidia,pins = "usb_vbus_en0_pcc4"; |
| nvidia,function = "usb"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| usb_vbus_en1_pcc5 { |
| nvidia,pins = "usb_vbus_en1_pcc5"; |
| nvidia,function = "usb"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_ENABLE>; |
| }; |
| dp_hpd0_pcc6 { |
| nvidia,pins = "dp_hpd0_pcc6"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pcc7 { |
| nvidia,pins = "pcc7"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| nvidia,io-hv = <TEGRA_PIN_DISABLE>; |
| }; |
| spi2_cs1_pdd0 { |
| nvidia,pins = "spi2_cs1_pdd0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| qspi_sck_pee0 { |
| nvidia,pins = "qspi_sck_pee0"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| qspi_cs_n_pee1 { |
| nvidia,pins = "qspi_cs_n_pee1"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| qspi_io0_pee2 { |
| nvidia,pins = "qspi_io0_pee2"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| qspi_io1_pee3 { |
| nvidia,pins = "qspi_io1_pee3"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| qspi_io2_pee4 { |
| nvidia,pins = "qspi_io2_pee4"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| qspi_io3_pee5 { |
| nvidia,pins = "qspi_io3_pee5"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| core_pwr_req { |
| nvidia,pins = "core_pwr_req"; |
| nvidia,function = "core"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| cpu_pwr_req { |
| nvidia,pins = "cpu_pwr_req"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_int_n { |
| nvidia,pins = "pwr_int_n"; |
| nvidia,function = "pmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| clk_32k_in { |
| nvidia,pins = "clk_32k_in"; |
| nvidia,function = "clk"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| jtag_rtck { |
| nvidia,pins = "jtag_rtck"; |
| nvidia,function = "jtag"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| clk_req { |
| nvidia,pins = "clk_req"; |
| nvidia,function = "rsvd1"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| shutdown { |
| nvidia,pins = "shutdown"; |
| nvidia,function = "shutdown"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| }; |
| }; |
| |
| serial@70006000 { |
| status = "okay"; |
| }; |
| |
| i2c@7000d000 { |
| status = "okay"; |
| clock-frequency = <400000>; |
| |
| max77620: max77620@3c { |
| compatible = "maxim,max77620"; |
| reg = <0x3c>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&max77620_default>; |
| |
| max77620_default: pinmux@0 { |
| pin_gpio0 { |
| pins = "gpio0"; |
| function = "gpio"; |
| }; |
| |
| pin_gpio1 { |
| pins = "gpio1"; |
| function = "fps-out"; |
| drive-push-pull = <1>; |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| maxim,active-fps-power-up-slot = <7>; |
| maxim,active-fps-power-down-slot = <0>; |
| }; |
| |
| pin_gpio2_3 { |
| pins = "gpio2", "gpio3"; |
| function = "fps-out"; |
| drive-open-drain = <1>; |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| }; |
| |
| pin_gpio4 { |
| pins = "gpio4"; |
| function = "32k-out1"; |
| }; |
| |
| pin_gpio5_6_7 { |
| pins = "gpio5", "gpio6", "gpio7"; |
| function = "gpio"; |
| drive-push-pull = <1>; |
| }; |
| |
| pin_gpio2 { |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| }; |
| |
| pin_gpio3 { |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| }; |
| }; |
| |
| spmic-default-output-high { |
| gpio-hog; |
| output-high; |
| gpios = <2 GPIO_ACTIVE_HIGH 7 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| fps { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| fps0 { |
| reg = <0>; |
| maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; |
| }; |
| |
| fps1 { |
| reg = <1>; |
| maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; |
| maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; |
| }; |
| |
| fps2 { |
| reg = <2>; |
| maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; |
| }; |
| }; |
| |
| regulators { |
| in-ldo0-1-supply = <&max77620_sd2>; |
| in-ldo7-8-supply = <&max77620_sd2>; |
| |
| max77620_sd0: sd0 { |
| regulator-name = "vdd-core"; |
| regulator-enable-ramp-delay = <146>; |
| regulator-min-microvolt = <600000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-ramp-delay = <27500>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-power-up-slot = <0>; |
| maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| }; |
| |
| max77620_sd1: sd1 { |
| regulator-name = "vddio-ddr"; |
| regulator-enable-ramp-delay = <130>; |
| regulator-ramp-delay = <27500>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| }; |
| |
| max77620_sd2: sd2 { |
| regulator-name = "vdd-pre-reg"; |
| regulator-enable-ramp-delay = <176>; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-ramp-delay = <27500>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_sd3: sd3 { |
| regulator-name = "vdd-1v8"; |
| regulator-enable-ramp-delay = <242>; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-ramp-delay = <27500>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| }; |
| |
| max77620_ldo0: ldo0 { |
| regulator-name = "avdd-sys"; |
| regulator-enable-ramp-delay = <26>; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-ramp-delay = <100000>; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo1: ldo1 { |
| regulator-name = "vdd-pex"; |
| regulator-enable-ramp-delay = <22>; |
| regulator-min-microvolt = <1075000>; |
| regulator-max-microvolt = <1075000>; |
| regulator-ramp-delay = <100000>; |
| regulator-always-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo2: ldo2 { |
| regulator-name = "vddio-sdmmc3"; |
| regulator-enable-ramp-delay = <62>; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-ramp-delay = <100000>; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo3: ldo3 { |
| regulator-name = "vdd-3v3-eth"; |
| regulator-enable-ramp-delay = <50>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-ramp-delay = <100000>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo4: ldo4 { |
| regulator-name = "vdd-rtc"; |
| regulator-enable-ramp-delay = <22>; |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <850000>; |
| regulator-ramp-delay = <100000>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| }; |
| |
| max77620_ldo5: ldo5 { |
| regulator-name = "avdd-ts-hv"; |
| regulator-enable-ramp-delay = <62>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-ramp-delay = <100000>; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo6: ldo6 { |
| regulator-name = "vdd-ts"; |
| regulator-enable-ramp-delay = <36>; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-ramp-delay = <100000>; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo7: ldo7 { |
| regulator-name = "vdd-gen-pll-edp"; |
| regulator-enable-ramp-delay = <24>; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| regulator-ramp-delay = <100000>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>; |
| }; |
| |
| max77620_ldo8: ldo8 { |
| regulator-name = "vdd-hdmi-dp"; |
| regulator-enable-ramp-delay = <22>; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| regulator-ramp-delay = <100000>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| }; |
| }; |
| }; |
| }; |
| |
| pmc@7000e400 { |
| nvidia,invert-interrupt; |
| nvidia,suspend-mode = <0>; |
| nvidia,cpu-pwr-good-time = <0>; |
| nvidia,cpu-pwr-off-time = <0>; |
| nvidia,core-pwr-good-time = <4587 3876>; |
| nvidia,core-pwr-off-time = <39065>; |
| nvidia,core-power-req-active-high; |
| nvidia,sys-clock-req-active-high; |
| status = "okay"; |
| }; |
| |
| sdhci@700b0600 { |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| clocks { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clk32k_in: clock@0 { |
| compatible = "fixed-clock"; |
| reg = <0>; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| status = "okay"; |
| |
| power { |
| debounce-interval = <30>; |
| gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; |
| label = "Power"; |
| linux,code = <KEY_POWER>; |
| wakeup-event-action = <EV_ACT_ASSERTED>; |
| wakeup-source; |
| }; |
| }; |
| |
| cpus { |
| cpu@0 { |
| enable-method = "psci"; |
| }; |
| |
| cpu@1 { |
| enable-method = "psci"; |
| }; |
| |
| cpu@2 { |
| enable-method = "psci"; |
| }; |
| |
| cpu@3 { |
| enable-method = "psci"; |
| }; |
| |
| idle-states { |
| cpu-sleep { |
| status = "okay"; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| device_type = "fixed-regulators"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| battery_reg: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "vdd-ac-bat"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-always-on; |
| }; |
| |
| vdd_3v3: regulator@1 { |
| compatible = "regulator-fixed"; |
| reg = <1>; |
| regulator-name = "vdd-3v3"; |
| regulator-enable-ramp-delay = <160>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| |
| gpio = <&max77620 3 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| max77620_gpio7: regulator@2 { |
| compatible = "regulator-fixed"; |
| reg = <2>; |
| regulator-name = "max77620-gpio7"; |
| regulator-enable-ramp-delay = <240>; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| vin-supply = <&max77620_ldo0>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| gpio = <&max77620 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| lcd_bl_en: regulator@3 { |
| compatible = "regulator-fixed"; |
| reg = <3>; |
| regulator-name = "lcd-bl-en"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| |
| gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| en_vdd_sd: regulator@4 { |
| compatible = "regulator-fixed"; |
| reg = <4>; |
| regulator-name = "en-vdd-sd"; |
| regulator-enable-ramp-delay = <472>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| vin-supply = <&vdd_3v3>; |
| |
| gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| en_vdd_cam: regulator@5 { |
| compatible = "regulator-fixed"; |
| reg = <5>; |
| regulator-name = "en-vdd-cam"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| |
| gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| vdd_sys_boost: regulator@6 { |
| compatible = "regulator-fixed"; |
| reg = <6>; |
| regulator-name = "vdd-sys-boost"; |
| regulator-enable-ramp-delay = <3090>; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-always-on; |
| |
| gpio = <&max77620 1 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| vdd_hdmi: regulator@7 { |
| compatible = "regulator-fixed"; |
| reg = <7>; |
| regulator-name = "vdd-hdmi"; |
| regulator-enable-ramp-delay = <468>; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| vin-supply = <&vdd_sys_boost>; |
| regulator-boot-on; |
| |
| gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| en_vdd_cpu_fixed: regulator@8 { |
| compatible = "regulator-fixed"; |
| reg = <8>; |
| regulator-name = "vdd-cpu-fixed"; |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <1000000>; |
| }; |
| |
| vdd_aux_3v3: regulator@9 { |
| compatible = "regulator-fixed"; |
| reg = <9>; |
| regulator-name = "aux-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| vdd_snsr_pm: regulator@10 { |
| compatible = "regulator-fixed"; |
| reg = <10>; |
| regulator-name = "snsr_pm"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| |
| enable-active-high; |
| }; |
| |
| vdd_usb_5v0: regulator@11 { |
| compatible = "regulator-fixed"; |
| reg = <11>; |
| status = "disabled"; |
| regulator-name = "vdd-usb-5v0"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| vin-supply = <&vdd_3v3>; |
| |
| enable-active-high; |
| }; |
| |
| vdd_cdc_1v2_aud: regulator@101 { |
| compatible = "regulator-fixed"; |
| reg = <101>; |
| status = "disabled"; |
| regulator-name = "vdd_cdc_1v2_aud"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| startup-delay-us = <250000>; |
| |
| enable-active-high; |
| }; |
| |
| vdd_disp_3v0: regulator@12 { |
| compatible = "regulator-fixed"; |
| reg = <12>; |
| regulator-name = "vdd-disp-3v0"; |
| regulator-enable-ramp-delay = <232>; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-always-on; |
| |
| gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| vdd_fan: regulator@13 { |
| compatible = "regulator-fixed"; |
| reg = <13>; |
| regulator-name = "vdd-fan"; |
| regulator-enable-ramp-delay = <284>; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| |
| gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| usb_vbus1: regulator@14 { |
| compatible = "regulator-fixed"; |
| reg = <14>; |
| regulator-name = "usb-vbus1"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| |
| gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| gpio-open-drain; |
| }; |
| |
| usb_vbus2: regulator@15 { |
| compatible = "regulator-fixed"; |
| reg = <15>; |
| regulator-name = "usb-vbus2"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| |
| gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| gpio-open-drain; |
| }; |
| |
| vdd_3v3_eth: regulator@16 { |
| compatible = "regulator-fixed"; |
| reg = <16>; |
| regulator-name = "vdd-3v3-eth-a02"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| |
| gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| gpio-open-drain; |
| }; |
| }; |
| }; |
