| // SPDX-License-Identifier: GPL-2.0+ OR MIT |
| /* |
| * Apple T8103 "M1" SoC |
| * |
| * Other names: H13G, "Tonga" |
| * |
| * Copyright The Asahi Linux Contributors |
| */ |
| |
| #include <dt-bindings/interrupt-controller/apple-aic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/pinctrl/apple.h> |
| |
| / { |
| compatible = "apple,t8103", "apple,arm-platform"; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "apple,icestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x0>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "apple,icestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x1>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "apple,icestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x2>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "apple,icestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x3>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu4: cpu@10100 { |
| compatible = "apple,firestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x10100>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu5: cpu@10101 { |
| compatible = "apple,firestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x10101>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu6: cpu@10102 { |
| compatible = "apple,firestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x10102>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| |
| cpu7: cpu@10103 { |
| compatible = "apple,firestorm"; |
| device_type = "cpu"; |
| reg = <0x0 0x10103>; |
| enable-method = "spin-table"; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&aic>; |
| interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; |
| interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| clk24: clock-24m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "clk24"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| ranges; |
| nonposted-mmio; |
| |
| serial0: serial@235200000 { |
| compatible = "apple,s5l-uart"; |
| reg = <0x2 0x35200000 0x0 0x1000>; |
| reg-io-width = <4>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; |
| /* |
| * TODO: figure out the clocking properly, there may |
| * be a third selectable clock. |
| */ |
| clocks = <&clk24>, <&clk24>; |
| clock-names = "uart", "clk_uart_baud0"; |
| status = "disabled"; |
| }; |
| |
| aic: interrupt-controller@23b100000 { |
| compatible = "apple,t8103-aic", "apple,aic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x2 0x3b100000 0x0 0x8000>; |
| }; |
| |
| pinctrl_ap: pinctrl@23c100000 { |
| compatible = "apple,t8103-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x3c100000 0x0 0x100000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_ap 0 0 212>; |
| apple,npins = <212>; |
| |
| interrupt-controller; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; |
| |
| pcie_pins: pcie-pins { |
| pinmux = <APPLE_PINMUX(150, 1)>, |
| <APPLE_PINMUX(151, 1)>, |
| <APPLE_PINMUX(32, 1)>; |
| }; |
| }; |
| |
| pinctrl_aop: pinctrl@24a820000 { |
| compatible = "apple,t8103-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x4a820000 0x0 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_aop 0 0 42>; |
| apple,npins = <42>; |
| |
| interrupt-controller; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_nub: pinctrl@23d1f0000 { |
| compatible = "apple,t8103-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x3d1f0000 0x0 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_nub 0 0 23>; |
| apple,npins = <23>; |
| |
| interrupt-controller; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pinctrl_smc: pinctrl@23e820000 { |
| compatible = "apple,t8103-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x3e820000 0x0 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_smc 0 0 16>; |
| apple,npins = <16>; |
| |
| interrupt-controller; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie0_dart_0: dart@681008000 { |
| compatible = "apple,t8103-dart"; |
| reg = <0x6 0x81008000 0x0 0x4000>; |
| #iommu-cells = <1>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie0_dart_1: dart@682008000 { |
| compatible = "apple,t8103-dart"; |
| reg = <0x6 0x82008000 0x0 0x4000>; |
| #iommu-cells = <1>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie0_dart_2: dart@683008000 { |
| compatible = "apple,t8103-dart"; |
| reg = <0x6 0x83008000 0x0 0x4000>; |
| #iommu-cells = <1>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie0: pcie@690000000 { |
| compatible = "apple,t8103-pcie", "apple,pcie"; |
| device_type = "pci"; |
| |
| reg = <0x6 0x90000000 0x0 0x1000000>, |
| <0x6 0x80000000 0x0 0x100000>, |
| <0x6 0x81000000 0x0 0x4000>, |
| <0x6 0x82000000 0x0 0x4000>, |
| <0x6 0x83000000 0x0 0x4000>; |
| reg-names = "config", "rc", "port0", "port1", "port2"; |
| |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; |
| |
| msi-controller; |
| msi-parent = <&pcie0>; |
| msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; |
| |
| |
| iommu-map = <0x100 &pcie0_dart_0 1 1>, |
| <0x200 &pcie0_dart_1 1 1>, |
| <0x300 &pcie0_dart_2 1 1>; |
| iommu-map-mask = <0xff00>; |
| |
| bus-range = <0 3>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, |
| <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; |
| |
| pinctrl-0 = <&pcie_pins>; |
| pinctrl-names = "default"; |
| |
| port00: pci@0,0 { |
| device_type = "pci"; |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| reset-gpios = <&pinctrl_ap 152 0>; |
| max-link-speed = <2>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &port00 0 0 0 0>, |
| <0 0 0 2 &port00 0 0 0 1>, |
| <0 0 0 3 &port00 0 0 0 2>, |
| <0 0 0 4 &port00 0 0 0 3>; |
| }; |
| |
| port01: pci@1,0 { |
| device_type = "pci"; |
| reg = <0x800 0x0 0x0 0x0 0x0>; |
| reset-gpios = <&pinctrl_ap 153 0>; |
| max-link-speed = <2>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &port01 0 0 0 0>, |
| <0 0 0 2 &port01 0 0 0 1>, |
| <0 0 0 3 &port01 0 0 0 2>, |
| <0 0 0 4 &port01 0 0 0 3>; |
| }; |
| |
| port02: pci@2,0 { |
| device_type = "pci"; |
| reg = <0x1000 0x0 0x0 0x0 0x0>; |
| reset-gpios = <&pinctrl_ap 33 0>; |
| max-link-speed = <1>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &port02 0 0 0 0>, |
| <0 0 0 2 &port02 0 0 0 1>, |
| <0 0 0 3 &port02 0 0 0 2>, |
| <0 0 0 4 &port02 0 0 0 3>; |
| }; |
| }; |
| }; |
| }; |
