| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Samsung SoC series UFS host controller Device Tree Bindings |
| |
| maintainers: |
| - Alim Akhtar <alim.akhtar@samsung.com> |
| |
| description: | |
| Each Samsung UFS host controller instance should have its own node. |
| |
| allOf: |
| - $ref: ufs-common.yaml |
| |
| properties: |
| compatible: |
| enum: |
| - samsung,exynos7-ufs |
| - samsung,exynosautov9-ufs |
| - samsung,exynosautov9-ufs-vh |
| |
| reg: |
| items: |
| - description: HCI register |
| - description: vendor specific register |
| - description: unipro register |
| - description: UFS protector register |
| |
| reg-names: |
| items: |
| - const: hci |
| - const: vs_hci |
| - const: unipro |
| - const: ufsp |
| |
| clocks: |
| items: |
| - description: ufs link core clock |
| - description: unipro main clock |
| |
| clock-names: |
| items: |
| - const: core_clk |
| - const: sclk_unipro_main |
| |
| phys: |
| maxItems: 1 |
| |
| phy-names: |
| const: ufs-phy |
| |
| samsung,sysreg: |
| $ref: '/schemas/types.yaml#/definitions/phandle-array' |
| description: Should be phandle/offset pair. The phandle to the syscon node |
| which indicates the FSYSx sysreg interface and the offset of |
| the control register for UFS io coherency setting. |
| |
| dma-coherent: true |
| |
| required: |
| - compatible |
| - reg |
| - phys |
| - phy-names |
| - clocks |
| - clock-names |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/exynos7-clk.h> |
| |
| ufs: ufs@15570000 { |
| compatible = "samsung,exynos7-ufs"; |
| reg = <0x15570000 0x100>, |
| <0x15570100 0x100>, |
| <0x15571000 0x200>, |
| <0x15572000 0x300>; |
| reg-names = "hci", "vs_hci", "unipro", "ufsp"; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clock_fsys1 ACLK_UFS20_LINK>, |
| <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; |
| clock-names = "core_clk", "sclk_unipro_main"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; |
| phys = <&ufs_phy>; |
| phy-names = "ufs-phy"; |
| }; |
| ... |
