arch/arm/boot/dts/dra72x.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on "omap4.dtsi"
 */

#include "dra7.dtsi"

/ {
	compatible = "ti,dra722", "ti,dra72", "ti,dra7";

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <&wakeupgen>;
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&dss {
	reg = <0x58000000 0x80>,
	      <0x58004054 0x4>,
	      <0x58004300 0x20>;
	reg-names = "dss", "pll1_clkctrl", "pll1";

	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
	clock-names = "fck", "video1_clk";
};

&mailbox5 {
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		ti,mbox-tx = <5 2 2>;
		ti,mbox-rx = <1 2 2>;
		status = "disabled";
	};
};

&mailbox6 {
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
};

&pcie1_rc {
	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};

&pcie1_ep {
	compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
};

&pcie2_rc {
	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};

&usb4_tm {
	status = "disabled";
};