Documentation/devicetree/bindings/net/mediatek-dwmac.txt

MediaTek DWMAC glue layer controller

This file documents platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.

The device node has following properties.

Required properties:
- compatible:  Should be "mediatek,mt2712-gmac" for MT2712 SoC
- reg:  Address and length of the register set for the device
- interrupts:  Should contain the MAC interrupts
- interrupt-names: Should contain a list of interrupt names corresponding to
	the interrupts in the interrupts property, if available.
	Should be "macirq" for the main MAC IRQ
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: The name of the clock listed in the clocks property. These are
	"axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
- mac-address: See ethernet.txt in the same directory
- phy-mode: See ethernet.txt in the same directory
- mediatek,pericfg: A phandle to the syscon node that control ethernet
	interface and timing delay.

Optional properties:
- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
	It should be defined for RGMII/MII interface.
	It should be defined for RMII interface when the reference clock is from MT2712 SoC.
- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
	It should be defined for RGMII/MII interface.
	It should be defined for RMII interface.
Both delay properties need to be a multiple of 170 for RGMII interface,
or will round down. Range 0~31*170.
Both delay properties need to be a multiple of 550 for MII/RMII interface,
or will round down. Range 0~31*550.

- mediatek,rmii-rxc: boolean property, if present indicates that the RMII
	reference clock, which is from external PHYs, is connected to RXC pin
	on MT2712 SoC.
	Otherwise, is connected to TXC pin.
- mediatek,rmii-clk-from-mac: boolean property, if present indicates that
	MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
- mediatek,txc-inverse: boolean property, if present indicates that
	1. tx clock will be inversed in MII/RGMII case,
	2. tx clock inside MAC will be inversed relative to reference clock
	   which is from external PHYs in RMII case, and it rarely happen.
	3. the reference clock, which outputs to TXC pin will be inversed in RMII case
	   when the reference clock is from MT2712 SoC.
- mediatek,rxc-inverse: boolean property, if present indicates that
	1. rx clock will be inversed in MII/RGMII case.
	2. reference clock will be inversed when arrived at MAC in RMII case, when
	   the reference clock is from external PHYs.
	3. the inside clock, which be sent to MAC, will be inversed in RMII case when
	   the reference clock is from MT2712 SoC.
- assigned-clocks: mac_main and ptp_ref clocks
- assigned-clock-parents: parent clocks of the assigned clocks

Example:
	eth: ethernet@1101c000 {
		compatible = "mediatek,mt2712-gmac";
		reg = <0 0x1101c000 0 0x1300>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "macirq";
		phy-mode ="rgmii-rxid";
		mac-address = [00 55 7b b5 7d f7];
		clock-names = "axi",
			      "apb",
			      "mac_main",
			      "ptp_ref",
			      "rmii_internal";
		clocks = <&pericfg CLK_PERI_GMAC>,
			 <&pericfg CLK_PERI_GMAC_PCLK>,
			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
			 <&topckgen CLK_TOP_ETHER_50M_SEL>,
			 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
				  <&topckgen CLK_TOP_ETHER_50M_SEL>,
				  <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
					 <&topckgen CLK_TOP_APLL1_D3>,
					 <&topckgen CLK_TOP_ETHERPLL_50M>;
		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
		mediatek,pericfg = <&pericfg>;
		mediatek,tx-delay-ps = <1530>;
		mediatek,rx-delay-ps = <1530>;
		mediatek,rmii-rxc;
		mediatek,txc-inverse;
		mediatek,rxc-inverse;
		snps,txpbl = <1>;
		snps,rxpbl = <1>;
		snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
		snps,reset-active-low;
	};