| OpenRISC Generic SoC |
| ==================== |
| |
| Boards and FPGA SoC's which support the OpenRISC standard platform. The |
| platform essentially follows the conventions of the OpenRISC architecture |
| specification, however some aspects, such as the boot protocol have been defined |
| by the Linux port. |
| |
| Required properties |
| ------------------- |
| - compatible: Must include "opencores,or1ksim" |
| |
| CPU nodes: |
| ---------- |
| A "cpus" node is required. Required properties: |
| - #address-cells: Must be 1. |
| - #size-cells: Must be 0. |
| A CPU sub-node is also required for at least CPU 0. Since the topology may |
| be probed via CPS, it is not necessary to specify secondary CPUs. Required |
| properties: |
| - compatible: Must be "opencores,or1200-rtlsvn481". |
| - reg: CPU number. |
| - clock-frequency: The CPU clock frequency in Hz. |
| Example: |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu@0 { |
| compatible = "opencores,or1200-rtlsvn481"; |
| reg = <0>; |
| clock-frequency = <20000000>; |
| }; |
| }; |
| |
| |
| Boot protocol |
| ------------- |
| The bootloader may pass the following arguments to the kernel: |
| - r3: address of a flattened device-tree blob or 0x0. |
