| [ |
| { |
| "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", |
| "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", |
| "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", |
| "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", |
| "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", |
| "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x40" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", |
| "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x80" |
| }, |
| { |
| "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
| "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xC7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
| "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Cycles with any input/output SSE or FP assist", |
| "Counter": "0,1,2,3", |
| "CounterHTOff": "0,1,2,3,4,5,6,7", |
| "CounterMask": "1", |
| "EventCode": "0xCA", |
| "EventName": "FP_ASSIST.ANY", |
| "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1e" |
| } |
| ] |
