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android-kvm / linux / 1cdc5ba06dcea1f1008c497fca34c42be9bc6a1d / . / arch / arm64 / boot / dts / nvidia / tegra234.dtsi
blob: 610207f3f9677061d48ba08d158532f3e074e490 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra234-clock.h>
#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra234-mc.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
/ {
compatible = "nvidia,tegra234";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
bus@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
aconnect@2900000 {
compatible = "nvidia,tegra234-aconnect",
"nvidia,tegra210-aconnect";
clocks = <&bpmp TEGRA234_CLK_APE>,
<&bpmp TEGRA234_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900000 0x02900000 0x200000>;
status = "disabled";
tegra_ahub: ahub@2900800 {
compatible = "nvidia,tegra234-ahub";
reg = <0x02900800 0x800>;
clocks = <&bpmp TEGRA234_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900800 0x02900800 0x11800>;
status = "disabled";
tegra_i2s1: i2s@2901000 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901000 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S1>,
<&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S1";
status = "disabled";
};
tegra_i2s2: i2s@2901100 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901100 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S2>,
<&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S2";
status = "disabled";
};
tegra_i2s3: i2s@2901200 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901200 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S3>,
<&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S3";
status = "disabled";
};
tegra_i2s4: i2s@2901300 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901300 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S4>,
<&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S4";
status = "disabled";
};
tegra_i2s5: i2s@2901400 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901400 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S5>,
<&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S5";
status = "disabled";
};
tegra_i2s6: i2s@2901500 {
compatible = "nvidia,tegra234-i2s",
"nvidia,tegra210-i2s";
reg = <0x2901500 0x100>;
clocks = <&bpmp TEGRA234_CLK_I2S6>,
<&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
clock-names = "i2s", "sync_input";
assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S6";
status = "disabled";
};
tegra_sfc1: sfc@2902000 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902000 0x200>;
sound-name-prefix = "SFC1";
status = "disabled";
};
tegra_sfc2: sfc@2902200 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902200 0x200>;
sound-name-prefix = "SFC2";
status = "disabled";
};
tegra_sfc3: sfc@2902400 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902400 0x200>;
sound-name-prefix = "SFC3";
status = "disabled";
};
tegra_sfc4: sfc@2902600 {
compatible = "nvidia,tegra234-sfc",
"nvidia,tegra210-sfc";
reg = <0x2902600 0x200>;
sound-name-prefix = "SFC4";
status = "disabled";
};
tegra_amx1: amx@2903000 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
reg = <0x2903000 0x100>;
sound-name-prefix = "AMX1";
status = "disabled";
};
tegra_amx2: amx@2903100 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
reg = <0x2903100 0x100>;
sound-name-prefix = "AMX2";
status = "disabled";
};
tegra_amx3: amx@2903200 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
reg = <0x2903200 0x100>;
sound-name-prefix = "AMX3";
status = "disabled";
};
tegra_amx4: amx@2903300 {
compatible = "nvidia,tegra234-amx",
"nvidia,tegra194-amx";
reg = <0x2903300 0x100>;
sound-name-prefix = "AMX4";
status = "disabled";
};
tegra_adx1: adx@2903800 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
reg = <0x2903800 0x100>;
sound-name-prefix = "ADX1";
status = "disabled";
};
tegra_adx2: adx@2903900 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
reg = <0x2903900 0x100>;
sound-name-prefix = "ADX2";
status = "disabled";
};
tegra_adx3: adx@2903a00 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
reg = <0x2903a00 0x100>;
sound-name-prefix = "ADX3";
status = "disabled";
};
tegra_adx4: adx@2903b00 {
compatible = "nvidia,tegra234-adx",
"nvidia,tegra210-adx";
reg = <0x2903b00 0x100>;
sound-name-prefix = "ADX4";
status = "disabled";
};
tegra_dmic1: dmic@2904000 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
reg = <0x2904000 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC1>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC1";
status = "disabled";
};
tegra_dmic2: dmic@2904100 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
reg = <0x2904100 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC2>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC2";
status = "disabled";
};
tegra_dmic3: dmic@2904200 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
reg = <0x2904200 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC3>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC3";
status = "disabled";
};
tegra_dmic4: dmic@2904300 {
compatible = "nvidia,tegra234-dmic",
"nvidia,tegra210-dmic";
reg = <0x2904300 0x100>;
clocks = <&bpmp TEGRA234_CLK_DMIC4>;
clock-names = "dmic";
assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC4";
status = "disabled";
};
tegra_dspk1: dspk@2905000 {
compatible = "nvidia,tegra234-dspk",
"nvidia,tegra186-dspk";
reg = <0x2905000 0x100>;
clocks = <&bpmp TEGRA234_CLK_DSPK1>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <12288000>;
sound-name-prefix = "DSPK1";
status = "disabled";
};
tegra_dspk2: dspk@2905100 {
compatible = "nvidia,tegra234-dspk",
"nvidia,tegra186-dspk";
reg = <0x2905100 0x100>;
clocks = <&bpmp TEGRA234_CLK_DSPK2>;
clock-names = "dspk";
assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
assigned-clock-rates = <12288000>;
sound-name-prefix = "DSPK2";
status = "disabled";
};
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra234-mvc",
"nvidia,tegra210-mvc";
reg = <0x290a000 0x200>;
sound-name-prefix = "MVC1";
status = "disabled";
};
tegra_mvc2: mvc@290a200 {
compatible = "nvidia,tegra234-mvc",
"nvidia,tegra210-mvc";
reg = <0x290a200 0x200>;
sound-name-prefix = "MVC2";
status = "disabled";
};
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra234-amixer",
"nvidia,tegra210-amixer";
reg = <0x290bb00 0x800>;
sound-name-prefix = "MIXER1";
status = "disabled";
};
tegra_admaif: admaif@290f000 {
compatible = "nvidia,tegra234-admaif",
"nvidia,tegra186-admaif";
reg = <0x0290f000 0x1000>;
dmas = <&adma 1>, <&adma 1>,
<&adma 2>, <&adma 2>,
<&adma 3>, <&adma 3>,
<&adma 4>, <&adma 4>,
<&adma 5>, <&adma 5>,
<&adma 6>, <&adma 6>,
<&adma 7>, <&adma 7>,
<&adma 8>, <&adma 8>,
<&adma 9>, <&adma 9>,
<&adma 10>, <&adma 10>,
<&adma 11>, <&adma 11>,
<&adma 12>, <&adma 12>,
<&adma 13>, <&adma 13>,
<&adma 14>, <&adma 14>,
<&adma 15>, <&adma 15>,
<&adma 16>, <&adma 16>,
<&adma 17>, <&adma 17>,
<&adma 18>, <&adma 18>,
<&adma 19>, <&adma 19>,
<&adma 20>, <&adma 20>;
dma-names = "rx1", "tx1",
"rx2", "tx2",
"rx3", "tx3",
"rx4", "tx4",
"rx5", "tx5",
"rx6", "tx6",
"rx7", "tx7",
"rx8", "tx8",
"rx9", "tx9",
"rx10", "tx10",
"rx11", "tx11",
"rx12", "tx12",
"rx13", "tx13",
"rx14", "tx14",
"rx15", "tx15",
"rx16", "tx16",
"rx17", "tx17",
"rx18", "tx18",
"rx19", "tx19",
"rx20", "tx20";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_APE>;
status = "disabled";
};
};
adma: dma-controller@2930000 {
compatible = "nvidia,tegra234-adma",
"nvidia,tegra186-adma";
reg = <0x02930000 0x20000>;
interrupt-parent = <&agic>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&bpmp TEGRA234_CLK_AHUB>;
clock-names = "d_audio";
status = "disabled";
};
agic: interrupt-controller@2a40000 {
compatible = "nvidia,tegra234-agic",
"nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x02a41000 0x1000>,
<0x02a42000 0x2000>;
interrupts = <GIC_SPI 145
(GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&bpmp TEGRA234_CLK_APE>;
clock-names = "clk";
status = "disabled";
};
};
misc@100000 {
compatible = "nvidia,tegra234-misc";
reg = <0x00100000 0xf000>,
<0x0010f000 0x1000>;
status = "okay";
};
gpio: gpio@2200000 {
compatible = "nvidia,tegra234-gpio";
reg-names = "security", "gpio";
reg = <0x02200000 0x10000>,
<0x02210000 0x10000>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
};
mc: memory-controller@2c00000 {
compatible = "nvidia,tegra234-mc";
reg = <0x02c00000 0x100000>,
<0x02b80000 0x040000>,
<0x01700000 0x100000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#interconnect-cells = <1>;
status = "okay";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
<0x02b80000 0x0 0x02b80000 0x0 0x040000>,
<0x02c00000 0x0 0x02c00000 0x0 0x100000>;
/*
* Bit 39 of addresses passing through the memory
* controller selects the XBAR format used when memory
* is accessed. This is used to transparently access
* memory in the XBAR format used by the discrete GPU
* (bit 39 set) or Tegra (bit 39 clear).
*
* As a consequence, the operating system must ensure
* that bit 39 is never used implicitly, for example
* via an I/O virtual address mapping of an IOMMU. If
* devices require access to the XBAR switch, their
* drivers must set this bit explicitly.
*
* Limit the DMA range for memory clients to [38:0].
*/
dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
emc: external-memory-controller@2c60000 {
compatible = "nvidia,tegra234-emc";
reg = <0x0 0x02c60000 0x0 0x90000>,
<0x0 0x01780000 0x0 0x80000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_EMC>;
clock-names = "emc";
status = "okay";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
};
};
uarta: serial@3100000 {
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x10000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_UARTA>;
clock-names = "serial";
resets = <&bpmp TEGRA234_RESET_UARTA>;
reset-names = "serial";
status = "disabled";
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x3160000 0x100>;
status = "disabled";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C1
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C1>;
reset-names = "i2c";
};
cam_i2c: i2c@3180000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x3180000 0x100>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C3
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C3>;
reset-names = "i2c";
};
dp_aux_ch1_i2c: i2c@3190000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x3190000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C4
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C4>;
reset-names = "i2c";
};
dp_aux_ch0_i2c: i2c@31b0000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x31b0000 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C6
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C6>;
reset-names = "i2c";
};
dp_aux_ch2_i2c: i2c@31c0000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x31c0000 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C7
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C7>;
reset-names = "i2c";
};
dp_aux_ch3_i2c: i2c@31e0000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x31e0000 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C9
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C9>;
reset-names = "i2c";
};
pwm1: pwm@3280000 {
compatible = "nvidia,tegra194-pwm",
"nvidia,tegra186-pwm";
reg = <0x3280000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_PWM1>;
clock-names = "pwm";
resets = <&bpmp TEGRA234_RESET_PWM1>;
reset-names = "pwm";
status = "disabled";
#pwm-cells = <2>;
};
mmc@3460000 {
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
reg = <0x03460000 0x20000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
<&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
<&bpmp TEGRA234_CLK_PLLC4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
resets = <&bpmp TEGRA234_RESET_SDMMC4>;
reset-names = "sdhci";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0x14>;
nvidia,dqs-trim = <40>;
supports-cqe;
status = "disabled";
};
hda@3510000 {
compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda";
reg = <0x3510000 0x10000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>;
clock-names = "hda", "hda2codec_2x";
resets = <&bpmp TEGRA234_RESET_HDA>,
<&bpmp TEGRA234_RESET_HDACODEC>;
reset-names = "hda", "hda2codec_2x";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
status = "disabled";
};
fuse@3810000 {
compatible = "nvidia,tegra234-efuse";
reg = <0x03810000 0x10000>;
clocks = <&bpmp TEGRA234_CLK_FUSE>;
clock-names = "fuse";
};
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x03c00000 0xa0000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "doorbell", "shared0", "shared1", "shared2",
"shared3", "shared4", "shared5", "shared6",
"shared7";
#mbox-cells = <2>;
};
smmu_niso1: iommu@8000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x8000000 0x1000000>,
<0x7000000 0x1000000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
stream-match-mask = <0x7f80>;
#global-interrupts = <2>;
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
status = "okay";
};
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
/*
* Shared interrupt 0 is routed only to AON/SPE, so
* we only have 4 shared interrupts for the CCPLEX.
*/
interrupt-names = "shared1", "shared2", "shared3", "shared4";
#mbox-cells = <2>;
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra194-i2c";
reg = <0xc240000 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C2
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C2>;
reset-names = "i2c";
};
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra194-i2c";
reg = <0xc250000 0x100>;
nvidia,hw-instance-id = <0x7>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C8
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C8>;
reset-names = "i2c";
};
rtc@c2a0000 {
compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
reg = <0x0c2a0000 0x10000>;
interrupt-parent = <&pmc>;
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
clock-names = "rtc";
status = "disabled";
};
gpio_aon: gpio@c2f0000 {
compatible = "nvidia,tegra234-gpio-aon";
reg-names = "security", "gpio";
reg = <0x0c2f0000 0x1000>,
<0x0c2f1000 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
};
pmc: pmc@c360000 {
compatible = "nvidia,tegra234-pmc";
reg = <0x0c360000 0x10000>,
<0x0c370000 0x10000>,
<0x0c380000 0x10000>,
<0x0c390000 0x10000>,
<0x0c3a0000 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch", "misc";
#interrupt-cells = <2>;
interrupt-controller;
};
gic: interrupt-controller@f400000 {
compatible = "arm,gic-v3";
reg = <0x0f400000 0x010000>, /* GICD */
<0x0f440000 0x200000>; /* GICR */
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#redistributor-regions = <1>;
#interrupt-cells = <3>;
interrupt-controller;
};
smmu_iso: iommu@10000000{
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x10000000 0x1000000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
status = "okay";
};
smmu_niso0: iommu@12000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x12000000 0x1000000>,
<0x11000000 0x1000000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
stream-match-mask = <0x7f80>;
#global-interrupts = <2>;
#iommu-cells = <1>;
nvidia,memory-controller = <&mc>;
status = "okay";
};
};
ccplex@e000000 {
compatible = "nvidia,tegra234-ccplex-cluster";
reg = <0x0 0x0e000000 0x0 0x5ffff>;
nvidia,bpmp = <&bpmp>;
status = "okay";
};
sram@40000000 {
compatible = "nvidia,tegra234-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x80000>;
cpu_bpmp_tx: sram@70000 {
reg = <0x70000 0x1000>;
label = "cpu-bpmp-tx";
pool;
};
cpu_bpmp_rx: sram@71000 {
reg = <0x71000 0x1000>;
label = "cpu-bpmp-rx";
pool;
};
};
bpmp: bpmp {
compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0_0: cpu@0 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00000>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_0>;
};
cpu0_1: cpu@100 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00100>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_1>;
};
cpu0_2: cpu@200 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00200>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_2>;
};
cpu0_3: cpu@300 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x00300>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c0_3>;
};
cpu1_0: cpu@10000 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10000>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_0>;
};
cpu1_1: cpu@10100 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10100>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_1>;
};
cpu1_2: cpu@10200 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10200>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_2>;
};
cpu1_3: cpu@10300 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x10300>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c1_3>;
};
cpu2_0: cpu@20000 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20000>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_0>;
};
cpu2_1: cpu@20100 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20100>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_1>;
};
cpu2_2: cpu@20200 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20200>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_2>;
};
cpu2_3: cpu@20300 {
compatible = "arm,cortex-a78";
device_type = "cpu";
reg = <0x20300>;
enable-method = "psci";
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2c2_3>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0_0>;
};
core1 {
cpu = <&cpu0_1>;
};
core2 {
cpu = <&cpu0_2>;
};
core3 {
cpu = <&cpu0_3>;
};
};
cluster1 {
core0 {
cpu = <&cpu1_0>;
};
core1 {
cpu = <&cpu1_1>;
};
core2 {
cpu = <&cpu1_2>;
};
core3 {
cpu = <&cpu1_3>;
};
};
cluster2 {
core0 {
cpu = <&cpu2_0>;
};
core1 {
cpu = <&cpu2_1>;
};
core2 {
cpu = <&cpu2_2>;
};
core3 {
cpu = <&cpu2_3>;
};
};
};
l2c0_0: l2-cache00 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c0_1: l2-cache01 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c0_2: l2-cache02 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c0_3: l2-cache03 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c0>;
};
l2c1_0: l2-cache10 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c1_1: l2-cache11 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c1_2: l2-cache12 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c1_3: l2-cache13 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c1>;
};
l2c2_0: l2-cache20 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l2c2_1: l2-cache21 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l2c2_2: l2-cache22 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l2c2_3: l2-cache23 {
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
next-level-cache = <&l3c2>;
};
l3c0: l3-cache0 {
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
};
l3c1: l3-cache1 {
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
};
l3c2: l3-cache2 {
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
};
};
pmu {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
psci {
compatible = "arm,psci-1.0";
status = "okay";
method = "smc";
};
tcu: serial {
compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
mbox-names = "rx", "tx";
status = "disabled";
};
sound {
status = "disabled";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>;
clock-names = "pll_a", "plla_out0";
assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <0>,
<&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
always-on;
};
};