Documentation/devicetree/bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 BayLibre, SAS
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |
  The Amlogic Meson Synopsys Designware Integration is composed of
  - A Synopsys DesignWare MIPI DSI Host Controller IP
  - A TOP control block controlling the Clocks & Resets of the IP

allOf:
  - $ref: dsi-controller.yaml#

properties:
  compatible:
    enum:
      - amlogic,meson-g12a-dw-mipi-dsi

  reg:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 4

  clock-names:
    minItems: 3
    items:
      - const: pclk
      - const: bit
      - const: px
      - const: meas

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: top

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: dphy

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input node to receive pixel data.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: DSI output node to panel.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - phys
  - phy-names
  - ports

unevaluatedProperties: false

examples:
  - |
    dsi@6000 {
          compatible = "amlogic,meson-g12a-dw-mipi-dsi";
          reg = <0x6000 0x400>;
          resets = <&reset_top>;
          reset-names = "top";
          clocks = <&clk_pclk>, <&bit_clk>, <&clk_px>;
          clock-names = "pclk", "bit", "px";
          phys = <&mipi_dphy>;
          phy-names = "dphy";

          ports {
              #address-cells = <1>;
              #size-cells = <0>;

              /* VPU VENC Input */
              mipi_dsi_venc_port: port@0 {
                  reg = <0>;

                  mipi_dsi_in: endpoint {
                       remote-endpoint = <&dpi_out>;
                  };
              };

              /* DSI Output */
              mipi_dsi_panel_port: port@1 {
                  reg = <1>;

                  mipi_out_panel: endpoint {
                      remote-endpoint = <&mipi_in_panel>;
                  };
              };
          };
    };