Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L Display Unit (DU)

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
  and RZ/V2L SoCs.

properties:
  compatible:
    oneOf:
      - enum:
          - renesas,r9a07g044-du # RZ/G2{L,LC}
      - items:
          - enum:
              - renesas,r9a07g054-du    # RZ/V2L
          - const: renesas,r9a07g044-du # RZ/G2L fallback

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Main clock
      - description: Register access clock
      - description: Video clock

  clock-names:
    items:
      - const: aclk
      - const: pclk
      - const: vclk

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      The connections to the DU output video ports are modeled using the OF
      graph bindings. The number of ports and their assignment are
      model-dependent. Each port shall have a single endpoint.

    patternProperties:
      "^port@[0-1]$":
        $ref: /schemas/graph.yaml#/properties/port
        unevaluatedProperties: false

    required:
      - port@0

    unevaluatedProperties: false

  renesas,vsps:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle to VSP instance that serves the DU channel
        - description: Channel index identifying the LIF instance in that VSP
    description:
      A list of phandle and channel index tuples to the VSPs that handle the
      memory interfaces for the DU channels.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - power-domains
  - ports
  - renesas,vsps

additionalProperties: false

examples:
  # RZ/G2L DU
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display@10890000 {
        compatible = "renesas,r9a07g044-du";
        reg = <0x10890000 0x10000>;
        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
        clock-names = "aclk", "pclk", "vclk";
        resets = <&cpg R9A07G044_LCDC_RESET_N>;
        power-domains = <&cpg>;

        renesas,vsps = <&vspd0 0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };
            port@1 {
                reg = <1>;
            };
        };
    };

...