| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC6_CFG_REGS_H_ |
| #define ASIC_REG_TPC6_CFG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC6_CFG (Prototype: TPC) |
| ***************************************** |
| */ |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF86418 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF8641C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF86420 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF86424 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86428 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF8642C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF86430 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86434 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF86438 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF8643C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86440 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86444 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF86448 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF8644C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF86450 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86454 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86458 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF8645C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF86460 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF86464 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86468 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF8646C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF86470 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86474 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF86478 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF8647C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86480 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86484 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF86488 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF8648C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF86490 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF86494 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86498 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF8649C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF864A0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF864A4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF864A8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF864AC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF864B0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF864B4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF864B8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF864BC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF864C0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF864C4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF864C8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF864CC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF864D0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF864D4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864D8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864DC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF864E0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864E4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864E8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864EC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864F0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864F4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864F8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF864FC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF86500 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF86504 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF86508 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF8650C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF86510 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF86514 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF86518 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF8651C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF86520 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF86524 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF86528 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF8652C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF86530 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF86534 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF86538 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF8653C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF86540 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF86544 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF86548 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF8654C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF86550 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF86554 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86558 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF8655C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF86560 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86564 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF86568 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF8656C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86570 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86574 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF86578 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF8657C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF86580 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86584 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86588 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF8658C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF86590 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF86594 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86598 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF8659C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF865A0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF865A4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF865A8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF865AC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF865B0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF865B4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF865B8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF865BC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF865C0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF865C4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF865C8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF865CC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF865D0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF865D4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF865D8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF865DC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF865E0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF865E4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF865E8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF865EC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF865F0 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF865F4 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF865F8 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF865FC |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF86600 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF86604 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86608 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF8660C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF86610 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86614 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF86618 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF8661C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86620 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86624 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF86628 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF8662C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF86630 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF86634 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF86638 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF8663C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF86640 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF86644 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF86648 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF8664C |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF86650 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF86654 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF86658 |
| |
| #define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF8665C |
| |
| #define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86660 |
| |
| #define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF86664 |
| |
| #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86668 |
| |
| #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF8666C |
| |
| #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86670 |
| |
| #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF86674 |
| |
| #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF86678 |
| |
| #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF8667C |
| |
| #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF86680 |
| |
| #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF86684 |
| |
| #define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF86688 |
| |
| #define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF8668C |
| |
| #define mmTPC6_CFG_KERNEL_SRF_0 0xF86690 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_1 0xF86694 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_2 0xF86698 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_3 0xF8669C |
| |
| #define mmTPC6_CFG_KERNEL_SRF_4 0xF866A0 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_5 0xF866A4 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_6 0xF866A8 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_7 0xF866AC |
| |
| #define mmTPC6_CFG_KERNEL_SRF_8 0xF866B0 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_9 0xF866B4 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_10 0xF866B8 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_11 0xF866BC |
| |
| #define mmTPC6_CFG_KERNEL_SRF_12 0xF866C0 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_13 0xF866C4 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_14 0xF866C8 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_15 0xF866CC |
| |
| #define mmTPC6_CFG_KERNEL_SRF_16 0xF866D0 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_17 0xF866D4 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_18 0xF866D8 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_19 0xF866DC |
| |
| #define mmTPC6_CFG_KERNEL_SRF_20 0xF866E0 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_21 0xF866E4 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_22 0xF866E8 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_23 0xF866EC |
| |
| #define mmTPC6_CFG_KERNEL_SRF_24 0xF866F0 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_25 0xF866F4 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_26 0xF866F8 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_27 0xF866FC |
| |
| #define mmTPC6_CFG_KERNEL_SRF_28 0xF86700 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_29 0xF86704 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_30 0xF86708 |
| |
| #define mmTPC6_CFG_KERNEL_SRF_31 0xF8670C |
| |
| #define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF86710 |
| |
| #define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86714 |
| |
| #define mmTPC6_CFG_RESERVED_DESC_END 0xF86738 |
| |
| #define mmTPC6_CFG_ROUND_CSR 0xF867FC |
| |
| #define mmTPC6_CFG_TBUF_BASE_ADDR_LOW 0xF86800 |
| |
| #define mmTPC6_CFG_TBUF_BASE_ADDR_HIGH 0xF86804 |
| |
| #define mmTPC6_CFG_SEMAPHORE 0xF86808 |
| |
| #define mmTPC6_CFG_VFLAGS 0xF8680C |
| |
| #define mmTPC6_CFG_SFLAGS 0xF86810 |
| |
| #define mmTPC6_CFG_LFSR_POLYNOM 0xF86818 |
| |
| #define mmTPC6_CFG_STATUS 0xF8681C |
| |
| #define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86820 |
| |
| #define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86824 |
| |
| #define mmTPC6_CFG_SM_BASE_ADDRESS_LOW 0xF86828 |
| |
| #define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8682C |
| |
| #define mmTPC6_CFG_TPC_CMD 0xF86830 |
| |
| #define mmTPC6_CFG_TPC_EXECUTE 0xF86838 |
| |
| #define mmTPC6_CFG_TPC_STALL 0xF8683C |
| |
| #define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86840 |
| |
| #define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86844 |
| |
| #define mmTPC6_CFG_MSS_CONFIG 0xF86854 |
| |
| #define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86858 |
| |
| #define mmTPC6_CFG_TPC_INTR_MASK 0xF8685C |
| |
| #define mmTPC6_CFG_TSB_CONFIG 0xF86860 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF86A18 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A1C |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A20 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF86A24 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A28 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A2C |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF86A30 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A34 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A38 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF86A3C |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A40 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A44 |
| |
| #define mmTPC6_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF86A48 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A4C |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A50 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A54 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A58 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A5C |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A60 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF86A64 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A68 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A6C |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF86A70 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A74 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A78 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF86A7C |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A80 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A84 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF86A88 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A8C |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A90 |
| |
| #define mmTPC6_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF86A94 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A98 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A9C |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86AA0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86AA4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86AA8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86AAC |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF86AB0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86AB4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86AB8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF86ABC |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86AC0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86AC4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF86AC8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86ACC |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86AD0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF86AD4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AD8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86ADC |
| |
| #define mmTPC6_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF86AE0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AE4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AE8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AEC |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AF0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AF4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86AF8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF86AFC |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86B00 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86B04 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF86B08 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86B0C |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86B10 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF86B14 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86B18 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86B1C |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF86B20 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86B24 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86B28 |
| |
| #define mmTPC6_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF86B2C |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86B30 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86B34 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86B38 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86B3C |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86B40 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86B44 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF86B48 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86B4C |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86B50 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF86B54 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B58 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B5C |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF86B60 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B64 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B68 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF86B6C |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B70 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B74 |
| |
| #define mmTPC6_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF86B78 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B7C |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B80 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B84 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B88 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B8C |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B90 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF86B94 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B98 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B9C |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF86BA0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86BA4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86BA8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF86BAC |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86BB0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86BB4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF86BB8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86BBC |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86BC0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF86BC4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86BC8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86BCC |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86BD0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86BD4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86BD8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86BDC |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF86BE0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86BE4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86BE8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF86BEC |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86BF0 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86BF4 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF86BF8 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86BFC |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86C00 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF86C04 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86C08 |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86C0C |
| |
| #define mmTPC6_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF86C10 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86C14 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86C18 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86C1C |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86C20 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86C24 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86C28 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF86C2C |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86C30 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86C34 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF86C38 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86C3C |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86C40 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF86C44 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86C48 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86C4C |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF86C50 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86C54 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86C58 |
| |
| #define mmTPC6_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF86C5C |
| |
| #define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86C60 |
| |
| #define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86C64 |
| |
| #define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86C68 |
| |
| #define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86C6C |
| |
| #define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86C70 |
| |
| #define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86C74 |
| |
| #define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86C78 |
| |
| #define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86C7C |
| |
| #define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86C80 |
| |
| #define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86C84 |
| |
| #define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86C88 |
| |
| #define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86C8C |
| |
| #define mmTPC6_CFG_QM_SRF_0 0xF86C90 |
| |
| #define mmTPC6_CFG_QM_SRF_1 0xF86C94 |
| |
| #define mmTPC6_CFG_QM_SRF_2 0xF86C98 |
| |
| #define mmTPC6_CFG_QM_SRF_3 0xF86C9C |
| |
| #define mmTPC6_CFG_QM_SRF_4 0xF86CA0 |
| |
| #define mmTPC6_CFG_QM_SRF_5 0xF86CA4 |
| |
| #define mmTPC6_CFG_QM_SRF_6 0xF86CA8 |
| |
| #define mmTPC6_CFG_QM_SRF_7 0xF86CAC |
| |
| #define mmTPC6_CFG_QM_SRF_8 0xF86CB0 |
| |
| #define mmTPC6_CFG_QM_SRF_9 0xF86CB4 |
| |
| #define mmTPC6_CFG_QM_SRF_10 0xF86CB8 |
| |
| #define mmTPC6_CFG_QM_SRF_11 0xF86CBC |
| |
| #define mmTPC6_CFG_QM_SRF_12 0xF86CC0 |
| |
| #define mmTPC6_CFG_QM_SRF_13 0xF86CC4 |
| |
| #define mmTPC6_CFG_QM_SRF_14 0xF86CC8 |
| |
| #define mmTPC6_CFG_QM_SRF_15 0xF86CCC |
| |
| #define mmTPC6_CFG_QM_SRF_16 0xF86CD0 |
| |
| #define mmTPC6_CFG_QM_SRF_17 0xF86CD4 |
| |
| #define mmTPC6_CFG_QM_SRF_18 0xF86CD8 |
| |
| #define mmTPC6_CFG_QM_SRF_19 0xF86CDC |
| |
| #define mmTPC6_CFG_QM_SRF_20 0xF86CE0 |
| |
| #define mmTPC6_CFG_QM_SRF_21 0xF86CE4 |
| |
| #define mmTPC6_CFG_QM_SRF_22 0xF86CE8 |
| |
| #define mmTPC6_CFG_QM_SRF_23 0xF86CEC |
| |
| #define mmTPC6_CFG_QM_SRF_24 0xF86CF0 |
| |
| #define mmTPC6_CFG_QM_SRF_25 0xF86CF4 |
| |
| #define mmTPC6_CFG_QM_SRF_26 0xF86CF8 |
| |
| #define mmTPC6_CFG_QM_SRF_27 0xF86CFC |
| |
| #define mmTPC6_CFG_QM_SRF_28 0xF86D00 |
| |
| #define mmTPC6_CFG_QM_SRF_29 0xF86D04 |
| |
| #define mmTPC6_CFG_QM_SRF_30 0xF86D08 |
| |
| #define mmTPC6_CFG_QM_SRF_31 0xF86D0C |
| |
| #define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86D10 |
| |
| #define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D14 |
| |
| #define mmTPC6_CFG_ARUSER 0xF86D18 |
| |
| #define mmTPC6_CFG_AWUSER 0xF86D1C |
| |
| #define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF86E00 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_PAT 0xF86E04 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF86E08 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF86E0C |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF86E10 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF86E14 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF86E18 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF86E1C |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF86E20 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF86E24 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF86E28 |
| |
| #define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF86E2C |
| |
| #endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ |
| |
