| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Support for Intel Camera Imaging ISP subsystem. |
| * Copyright (c) 2010-2015, Intel Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms and conditions of the GNU General Public License, |
| * version 2, as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| * more details. |
| */ |
| |
| #ifndef __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__ |
| #define __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__ |
| |
| #include "input_system_defs.h" /* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */ |
| |
| /* |
| * _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX, |
| * _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,... |
| */ |
| #include "css_receiver_2400_defs.h" |
| |
| #include "isp_capture_defs.h" |
| |
| #include "isp_acquisition_defs.h" |
| #include "input_system_ctrl_defs.h" |
| |
| struct target_cfg2400_s { |
| input_switch_cfg_channel_t input_switch_channel_cfg; |
| target_isp_cfg_t target_isp_cfg; |
| target_sp_cfg_t target_sp_cfg; |
| target_strm2mem_cfg_t target_strm2mem_cfg; |
| }; |
| |
| // Configuration of a channel. |
| struct channel_cfg_s { |
| u32 ch_id; |
| backend_channel_cfg_t backend_ch; |
| input_system_source_t source_type; |
| source_cfg_t source_cfg; |
| target_cfg2400_t target_cfg; |
| }; |
| |
| // Complete configuration for input system. |
| struct input_system_cfg2400_s { |
| input_system_source_t source_type; |
| input_system_config_flags_t source_type_flags; |
| //channel_cfg_t channel[N_CHANNELS]; |
| input_system_config_flags_t ch_flags[N_CHANNELS]; |
| // This is the place where the buffers' settings are collected, as given. |
| csi_cfg_t csi_value[N_CSI_PORTS]; |
| input_system_config_flags_t csi_flags[N_CSI_PORTS]; |
| |
| // Possible another struct for ib. |
| // This buffers set at the end, based on the all configurations. |
| isp2400_ib_buffer_t csi_buffer[N_CSI_PORTS]; |
| input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS]; |
| isp2400_ib_buffer_t acquisition_buffer_unique; |
| input_system_config_flags_t acquisition_buffer_unique_flags; |
| u32 unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS. |
| //uint32_t acq_allocated_ib_mem_words; |
| |
| input_system_connection_t multicast[N_CSI_PORTS]; |
| input_system_multiplex_t multiplexer; |
| input_system_config_flags_t multiplexer_flags; |
| |
| tpg_cfg_t tpg_value; |
| input_system_config_flags_t tpg_flags; |
| prbs_cfg_t prbs_value; |
| input_system_config_flags_t prbs_flags; |
| gpfifo_cfg_t gpfifo_value; |
| input_system_config_flags_t gpfifo_flags; |
| |
| input_switch_cfg_t input_switch_cfg; |
| |
| target_isp_cfg_t target_isp[N_CHANNELS]; |
| input_system_config_flags_t target_isp_flags[N_CHANNELS]; |
| target_sp_cfg_t target_sp[N_CHANNELS]; |
| input_system_config_flags_t target_sp_flags[N_CHANNELS]; |
| target_strm2mem_cfg_t target_strm2mem[N_CHANNELS]; |
| input_system_config_flags_t target_strm2mem_flags[N_CHANNELS]; |
| |
| input_system_config_flags_t session_flags; |
| |
| }; |
| |
| /* |
| * For each MIPI port |
| */ |
| #define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX |
| #define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX |
| #define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX |
| #define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX |
| #define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX |
| /* new regs for each MIPI port w.r.t. 2300 */ |
| #define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX |
| #define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX |
| #define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX |
| |
| /* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */ |
| /* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */ |
| #define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX |
| #define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX |
| #define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX |
| #define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX |
| #define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX |
| #define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX |
| #define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX |
| #define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX |
| #define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX |
| #define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX |
| #define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX |
| |
| /* Previously MIPI port regs, now 2x2 logical channel regs */ |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX |
| #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX |
| |
| /* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */ |
| #define _HRT_CSS_BE_OFFSET 448 |
| #define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET) |
| #define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET) |
| |
| #define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT |
| #define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT |
| |
| #define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX |
| #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX |
| #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS |
| |
| typedef enum { |
| MIPI_FORMAT_2400_RGB888 = 0, |
| MIPI_FORMAT_2400_RGB555, |
| MIPI_FORMAT_2400_RGB444, |
| MIPI_FORMAT_2400_RGB565, |
| MIPI_FORMAT_2400_RGB666, |
| MIPI_FORMAT_2400_RAW8, /* 5 */ |
| MIPI_FORMAT_2400_RAW10, |
| MIPI_FORMAT_2400_RAW6, |
| MIPI_FORMAT_2400_RAW7, |
| MIPI_FORMAT_2400_RAW12, |
| MIPI_FORMAT_2400_RAW14, /* 10 */ |
| MIPI_FORMAT_2400_YUV420_8, |
| MIPI_FORMAT_2400_YUV420_10, |
| MIPI_FORMAT_2400_YUV422_8, |
| MIPI_FORMAT_2400_YUV422_10, |
| MIPI_FORMAT_2400_CUSTOM0, /* 15 */ |
| MIPI_FORMAT_2400_YUV420_8_LEGACY, |
| MIPI_FORMAT_2400_EMBEDDED, |
| MIPI_FORMAT_2400_CUSTOM1, |
| MIPI_FORMAT_2400_CUSTOM2, |
| MIPI_FORMAT_2400_CUSTOM3, /* 20 */ |
| MIPI_FORMAT_2400_CUSTOM4, |
| MIPI_FORMAT_2400_CUSTOM5, |
| MIPI_FORMAT_2400_CUSTOM6, |
| MIPI_FORMAT_2400_CUSTOM7, |
| MIPI_FORMAT_2400_YUV420_8_SHIFT, /* 25 */ |
| MIPI_FORMAT_2400_YUV420_10_SHIFT, |
| MIPI_FORMAT_2400_RAW16, |
| MIPI_FORMAT_2400_RAW18, |
| N_MIPI_FORMAT_2400, |
| } mipi_format_2400_t; |
| |
| #define N_MIPI_FORMAT_CUSTOM 8 |
| |
| /* The number of stores for compressed format types */ |
| #define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) |
| |
| typedef enum { |
| RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT, |
| RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT, |
| RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT, |
| RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT, |
| RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT, |
| RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT, |
| RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT, |
| RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT, |
| RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT, |
| /* RX_IRQ_INFO_NO_ERR = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT, */ |
| RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT, |
| RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT, |
| RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT, |
| RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT, |
| RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT, |
| RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT, |
| RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT, |
| } rx_irq_info_t; |
| |
| /* NOTE: The base has already an offset of 0x0100 */ |
| static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { |
| 0x00000000UL, |
| 0x00000100UL, |
| 0x00000200UL |
| }; |
| |
| static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = { |
| 0x00001000UL, |
| 0x00002000UL, |
| 0x00003000UL, |
| 0x00004000UL, |
| 0x00005000UL, |
| 0x00009000UL, |
| 0x0000A000UL, |
| 0x0000B000UL, |
| 0x0000C000UL |
| }; |
| |
| #endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ |
