| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Mediatek AFE PCM controller for mt8195 |
| |
| maintainers: |
| - Trevor Wu <trevor.wu@mediatek.com> |
| |
| properties: |
| compatible: |
| const: mediatek,mt8195-audio |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| mediatek,topckgen: |
| $ref: "/schemas/types.yaml#/definitions/phandle" |
| description: The phandle of the mediatek topckgen controller |
| |
| power-domains: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: 26M clock |
| - description: audio pll1 clock |
| - description: audio pll2 clock |
| - description: clock divider for i2si1_mck |
| - description: clock divider for i2si2_mck |
| - description: clock divider for i2so1_mck |
| - description: clock divider for i2so2_mck |
| - description: clock divider for dptx_mck |
| - description: a1sys hoping clock |
| - description: audio intbus clock |
| - description: audio hires clock |
| - description: audio local bus clock |
| - description: mux for dptx_mck |
| - description: mux for i2so1_mck |
| - description: mux for i2so2_mck |
| - description: mux for i2si1_mck |
| - description: mux for i2si2_mck |
| - description: audio infra 26M clock |
| - description: infra bus clock |
| |
| clock-names: |
| items: |
| - const: clk26m |
| - const: apll1_ck |
| - const: apll2_ck |
| - const: apll12_div0 |
| - const: apll12_div1 |
| - const: apll12_div2 |
| - const: apll12_div3 |
| - const: apll12_div9 |
| - const: a1sys_hp_sel |
| - const: aud_intbus_sel |
| - const: audio_h_sel |
| - const: audio_local_bus_sel |
| - const: dptx_m_sel |
| - const: i2so1_m_sel |
| - const: i2so2_m_sel |
| - const: i2si1_m_sel |
| - const: i2si2_m_sel |
| - const: infra_ao_audio_26m_b |
| - const: scp_adsp_audiodsp |
| |
| mediatek,etdm-in1-chn-disabled: |
| $ref: /schemas/types.yaml#/definitions/uint8-array |
| maxItems: 24 |
| description: Specify which input channel should be disabled. |
| |
| mediatek,etdm-in2-chn-disabled: |
| $ref: /schemas/types.yaml#/definitions/uint8-array |
| maxItems: 16 |
| description: Specify which input channel should be disabled. |
| |
| patternProperties: |
| "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$": |
| description: Specify etdm in mclk output rate for always on case. |
| |
| "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$": |
| description: Specify etdm out mclk output rate for always on case. |
| |
| "^mediatek,etdm-in[1-2]-multi-pin-mode$": |
| type: boolean |
| description: if present, the etdm data mode is I2S. |
| |
| "^mediatek,etdm-out[1-3]-multi-pin-mode$": |
| type: boolean |
| description: if present, the etdm data mode is I2S. |
| |
| "^mediatek,etdm-in[1-2]-cowork-source$": |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| etdm modules can share the same external clock pin. Specify |
| which etdm clock source is required by this etdm in moudule. |
| enum: |
| - 0 # etdm1_in |
| - 1 # etdm2_in |
| - 2 # etdm1_out |
| - 3 # etdm2_out |
| |
| "^mediatek,etdm-out[1-2]-cowork-source$": |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| etdm modules can share the same external clock pin. Specify |
| which etdm clock source is required by this etdm out moudule. |
| enum: |
| - 0 # etdm1_in |
| - 1 # etdm2_in |
| - 2 # etdm1_out |
| - 3 # etdm2_out |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - mediatek,topckgen |
| - power-domains |
| - clocks |
| - clock-names |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| afe: mt8195-afe-pcm@10890000 { |
| compatible = "mediatek,mt8195-audio"; |
| reg = <0x10890000 0x10000>; |
| interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; |
| mediatek,topckgen = <&topckgen>; |
| power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO |
| clocks = <&clk26m>, |
| <&topckgen 163>, //CLK_TOP_APLL1 |
| <&topckgen 166>, //CLK_TOP_APLL2 |
| <&topckgen 233>, //CLK_TOP_APLL12_DIV0 |
| <&topckgen 234>, //CLK_TOP_APLL12_DIV1 |
| <&topckgen 235>, //CLK_TOP_APLL12_DIV2 |
| <&topckgen 236>, //CLK_TOP_APLL12_DIV3 |
| <&topckgen 238>, //CLK_TOP_APLL12_DIV9 |
| <&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL |
| <&topckgen 33>, //CLK_TOP_AUD_INTBUS_SEL |
| <&topckgen 34>, //CLK_TOP_AUDIO_H_SEL |
| <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS_SEL |
| <&topckgen 98>, //CLK_TOP_DPTX_M_SEL |
| <&topckgen 94>, //CLK_TOP_I2SO1_M_SEL |
| <&topckgen 95>, //CLK_TOP_I2SO2_M_SEL |
| <&topckgen 96>, //CLK_TOP_I2SI1_M_SEL |
| <&topckgen 97>, //CLK_TOP_I2SI2_M_SEL |
| <&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B |
| <&scp_adsp 0>; //CLK_SCP_ADSP_AUDIODSP |
| clock-names = "clk26m", |
| "apll1_ck", |
| "apll2_ck", |
| "apll12_div0", |
| "apll12_div1", |
| "apll12_div2", |
| "apll12_div3", |
| "apll12_div9", |
| "a1sys_hp_sel", |
| "aud_intbus_sel", |
| "audio_h_sel", |
| "audio_local_bus_sel", |
| "dptx_m_sel", |
| "i2so1_m_sel", |
| "i2so2_m_sel", |
| "i2si1_m_sel", |
| "i2si2_m_sel", |
| "infra_ao_audio_26m_b", |
| "scp_adsp_audiodsp"; |
| }; |
| |
| ... |
