| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ |
| #define ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_HMMU0_MMU |
| * (Prototype: MMU) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_ENABLE 0x408000C |
| |
| #define mmDCORE0_HMMU0_MMU_FORCE_ORDERING 0x4080010 |
| |
| #define mmDCORE0_HMMU0_MMU_FEATURE_ENABLE 0x4080014 |
| |
| #define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 0x4080018 |
| |
| #define mmDCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 0x408001C |
| |
| #define mmDCORE0_HMMU0_MMU_LOG2_DDR_SIZE 0x4080020 |
| |
| #define mmDCORE0_HMMU0_MMU_SCRAMBLER 0x4080024 |
| |
| #define mmDCORE0_HMMU0_MMU_MEM_INIT_BUSY 0x4080028 |
| |
| #define mmDCORE0_HMMU0_MMU_SPI_SEI_MASK 0x408002C |
| |
| #define mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE 0x4080030 |
| |
| #define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE 0x4080034 |
| |
| #define mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA 0x4080038 |
| |
| #define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE 0x408003C |
| |
| #define mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA 0x4080040 |
| |
| #define mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID 0x4080044 |
| |
| #define mmDCORE0_HMMU0_MMU_INTERRUPT_CLR 0x4080048 |
| |
| #define mmDCORE0_HMMU0_MMU_INTERRUPT_MASK 0x408004C |
| |
| #define mmDCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM 0x4080050 |
| |
| #define mmDCORE0_HMMU0_MMU_SPI_CAUSE_CLR 0x4080054 |
| |
| #define mmDCORE0_HMMU0_MMU_PIPE_CREDIT 0x4080058 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_BYPASS 0x408006C |
| |
| #define mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE 0x4080070 |
| |
| #define mmDCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG 0x40800A0 |
| |
| #define mmDCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT 0x40800D0 |
| |
| #define mmDCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT 0x40800F4 |
| |
| #define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB 0x40800F8 |
| |
| #define mmDCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB 0x40800FC |
| |
| #define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB 0x4080100 |
| |
| #define mmDCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB 0x4080104 |
| |
| #define mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE 0x4080108 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0 0x4080110 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_1 0x4080114 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_2 0x4080118 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_3 0x408011C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_4 0x4080120 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_5 0x4080124 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_6 0x4080128 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_7 0x408012C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0 0x4080140 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_1 0x4080144 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_2 0x4080148 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_3 0x408014C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_4 0x4080150 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_5 0x4080154 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_6 0x4080158 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_7 0x408015C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0 0x4080170 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_1 0x4080174 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_2 0x4080178 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_3 0x408017C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_4 0x4080180 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_5 0x4080184 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_6 0x4080188 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_7 0x408018C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0 0x40801A0 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_1 0x40801A4 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_2 0x40801A8 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_3 0x40801AC |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_4 0x40801B0 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_5 0x40801B4 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_6 0x40801B8 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_7 0x40801BC |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0 0x40801D0 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_1 0x40801D4 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_2 0x40801D8 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_3 0x40801DC |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_4 0x40801E0 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_5 0x40801E4 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_6 0x40801E8 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_7 0x40801EC |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0 0x4080200 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_1 0x4080204 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_2 0x4080208 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_3 0x408020C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_4 0x4080210 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_5 0x4080214 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_6 0x4080218 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_7 0x408021C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0 0x4080230 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_1 0x4080234 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_2 0x4080238 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_3 0x408023C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_4 0x4080240 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_5 0x4080244 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_6 0x4080248 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_7 0x408024C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0 0x4080260 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_1 0x4080264 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_2 0x4080268 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_3 0x408026C |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_4 0x4080270 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_5 0x4080274 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_6 0x4080278 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_7 0x408027C |
| |
| #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 0x4080290 |
| |
| #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 0x4080294 |
| |
| #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 0x4080298 |
| |
| #define mmDCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 0x408029C |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_VLD 0x4080300 |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 0x4080304 |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 0x4080308 |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_READ_VLD 0x408030C |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 0x4080310 |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 0x4080314 |
| |
| #define mmDCORE0_HMMU0_MMU_MMU_SRC_NUM 0x408031C |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_LSB 0x4080320 |
| |
| #define mmDCORE0_HMMU0_MMU_RAZWI_ADDR_MSB 0x4080324 |
| |
| #endif /* ASIC_REG_DCORE0_HMMU0_MMU_REGS_H_ */ |