| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ |
| #define ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW |
| * (Prototype: RANGE_REG_HBW) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 0x4142000 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_1 0x4142004 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_2 0x4142008 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_3 0x414200C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_4 0x4142010 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_5 0x4142014 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 0x4142018 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_1 0x414201C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_2 0x4142020 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_3 0x4142024 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_4 0x4142028 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_5 0x414202C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 0x4142030 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_1 0x4142034 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_2 0x4142038 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_3 0x414203C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_4 0x4142040 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_5 0x4142044 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 0x4142048 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_1 0x414204C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_2 0x4142050 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_3 0x4142054 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_4 0x4142058 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_5 0x414205C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 0x4142060 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_1 0x4142064 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_2 0x4142068 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_3 0x414206C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_4 0x4142070 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_5 0x4142074 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 0x4142078 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_1 0x414207C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_2 0x4142080 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_3 0x4142084 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_4 0x4142088 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_5 0x414208C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 0x4142090 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_1 0x4142094 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_2 0x4142098 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_3 0x414209C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_4 0x41420A0 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_5 0x41420A4 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 0x41420A8 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_1 0x41420AC |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_2 0x41420B0 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_3 0x41420B4 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_4 0x41420B8 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_5 0x41420BC |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 0x41420C0 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_1 0x41420C4 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_2 0x41420C8 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_3 0x41420CC |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 0x41420D0 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_1 0x41420D4 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_2 0x41420D8 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_3 0x41420DC |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 0x41420E0 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_1 0x41420E4 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_2 0x41420E8 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_3 0x41420EC |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 0x41420F0 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_1 0x41420F4 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_2 0x41420F8 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_3 0x41420FC |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 0x4142100 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_1 0x4142104 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_2 0x4142108 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_3 0x414210C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 0x4142110 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_1 0x4142114 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_2 0x4142118 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_3 0x414211C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 0x4142120 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_1 0x4142124 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_2 0x4142128 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_3 0x414212C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 0x4142130 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_1 0x4142134 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_2 0x4142138 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_3 0x414213C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_PCIE_EN 0x4142140 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_PCIE_EN 0x4142144 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AW 0x4142148 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AW 0x414214C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_HIT_AR 0x4142150 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_HIT_AR 0x4142154 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI 0x4142158 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO 0x414215C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI 0x4142160 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO 0x4142164 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY 0x4142168 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY 0x414216C |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED 0x4142170 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED 0x4142174 |
| |
| #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_RAZWI_ERR_RESP 0x4142178 |
| |
| #endif /* ASIC_REG_DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_REGS_H_ */ |