| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PDMA0_CORE_REGS_H_ |
| #define ASIC_REG_PDMA0_CORE_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PDMA0_CORE |
| * (Prototype: DMA_CORE) |
| ***************************************** |
| */ |
| |
| #define mmPDMA0_CORE_CFG_0 0x4C8B000 |
| |
| #define mmPDMA0_CORE_CFG_1 0x4C8B004 |
| |
| #define mmPDMA0_CORE_PROT 0x4C8B008 |
| |
| #define mmPDMA0_CORE_CKG 0x4C8B00C |
| |
| #define mmPDMA0_CORE_RD_GLBL 0x4C8B07C |
| |
| #define mmPDMA0_CORE_RD_HBW_MAX_OUTSTAND 0x4C8B080 |
| |
| #define mmPDMA0_CORE_RD_HBW_MAX_SIZE 0x4C8B084 |
| |
| #define mmPDMA0_CORE_RD_HBW_ARCACHE 0x4C8B088 |
| |
| #define mmPDMA0_CORE_RD_HBW_INFLIGHTS 0x4C8B090 |
| |
| #define mmPDMA0_CORE_RD_HBW_RATE_LIM_CFG 0x4C8B094 |
| |
| #define mmPDMA0_CORE_RD_LBW_MAX_OUTSTAND 0x4C8B0C0 |
| |
| #define mmPDMA0_CORE_RD_LBW_MAX_SIZE 0x4C8B0C4 |
| |
| #define mmPDMA0_CORE_RD_LBW_ARCACHE 0x4C8B0C8 |
| |
| #define mmPDMA0_CORE_RD_LBW_INFLIGHTS 0x4C8B0D0 |
| |
| #define mmPDMA0_CORE_RD_LBW_RATE_LIM_CFG 0x4C8B0D4 |
| |
| #define mmPDMA0_CORE_WR_HBW_MAX_OUTSTAND 0x4C8B100 |
| |
| #define mmPDMA0_CORE_WR_HBW_MAX_AWID 0x4C8B104 |
| |
| #define mmPDMA0_CORE_WR_HBW_AWCACHE 0x4C8B108 |
| |
| #define mmPDMA0_CORE_WR_HBW_INFLIGHTS 0x4C8B10C |
| |
| #define mmPDMA0_CORE_WR_HBW_RATE_LIM_CFG 0x4C8B110 |
| |
| #define mmPDMA0_CORE_WR_LBW_MAX_OUTSTAND 0x4C8B140 |
| |
| #define mmPDMA0_CORE_WR_LBW_MAX_AWID 0x4C8B144 |
| |
| #define mmPDMA0_CORE_WR_LBW_AWCACHE 0x4C8B148 |
| |
| #define mmPDMA0_CORE_WR_LBW_INFLIGHTS 0x4C8B14C |
| |
| #define mmPDMA0_CORE_WR_LBW_RATE_LIM_CFG 0x4C8B150 |
| |
| #define mmPDMA0_CORE_WR_COMP_MAX_OUTSTAND 0x4C8B180 |
| |
| #define mmPDMA0_CORE_WR_COMP_AWUSER 0x4C8B184 |
| |
| #define mmPDMA0_CORE_ERR_CFG 0x4C8B300 |
| |
| #define mmPDMA0_CORE_ERR_CAUSE 0x4C8B304 |
| |
| #define mmPDMA0_CORE_ERRMSG_ADDR_LO 0x4C8B308 |
| |
| #define mmPDMA0_CORE_ERRMSG_ADDR_HI 0x4C8B30C |
| |
| #define mmPDMA0_CORE_ERRMSG_WDATA 0x4C8B310 |
| |
| #define mmPDMA0_CORE_STS0 0x4C8B380 |
| |
| #define mmPDMA0_CORE_STS1 0x4C8B384 |
| |
| #define mmPDMA0_CORE_STS_RD_CTX_SEL 0x4C8B400 |
| |
| #define mmPDMA0_CORE_STS_RD_CTX_SIZE 0x4C8B404 |
| |
| #define mmPDMA0_CORE_STS_RD_CTX_BASE_LO 0x4C8B408 |
| |
| #define mmPDMA0_CORE_STS_RD_CTX_BASE_HI 0x4C8B40C |
| |
| #define mmPDMA0_CORE_STS_RD_CTX_ID 0x4C8B410 |
| |
| #define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_LO 0x4C8B414 |
| |
| #define mmPDMA0_CORE_STS_RD_HB_AXI_ADDR_HI 0x4C8B418 |
| |
| #define mmPDMA0_CORE_STS_RD_LB_AXI_ADDR 0x4C8B41C |
| |
| #define mmPDMA0_CORE_STS_WR_CTX_SEL 0x4C8B420 |
| |
| #define mmPDMA0_CORE_STS_WR_CTX_SIZE 0x4C8B424 |
| |
| #define mmPDMA0_CORE_STS_WR_CTX_BASE_LO 0x4C8B428 |
| |
| #define mmPDMA0_CORE_STS_WR_CTX_BASE_HI 0x4C8B42C |
| |
| #define mmPDMA0_CORE_STS_WR_CTX_ID 0x4C8B430 |
| |
| #define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_LO 0x4C8B434 |
| |
| #define mmPDMA0_CORE_STS_WR_HB_AXI_ADDR_HI 0x4C8B438 |
| |
| #define mmPDMA0_CORE_STS_WR_LB_AXI_ADDR 0x4C8B43C |
| |
| #define mmPDMA0_CORE_PWRLP_CFG 0x4C8B700 |
| |
| #define mmPDMA0_CORE_PWRLP_STS 0x4C8B704 |
| |
| #define mmPDMA0_CORE_DBG_DESC_CNT 0x4C8B710 |
| |
| #define mmPDMA0_CORE_DBG_STS 0x4C8B714 |
| |
| #define mmPDMA0_CORE_DBG_BUF_STS 0x4C8B718 |
| |
| #define mmPDMA0_CORE_DBG_RD_DESC_ID 0x4C8B720 |
| |
| #define mmPDMA0_CORE_DBG_WR_DESC_ID 0x4C8B724 |
| |
| #define mmPDMA0_CORE_APB_DMA_LBW_BASE 0x4C8B728 |
| |
| #define mmPDMA0_CORE_APB_MSTR_IF_LBW_BASE 0x4C8B72C |
| |
| #define mmPDMA0_CORE_E2E_CRED_ASYNC_CFG 0x4C8B730 |
| |
| #define mmPDMA0_CORE_DBG_APB_ENABLER 0x4C8BE1C |
| |
| #define mmPDMA0_CORE_L2H_CMPR_LO 0x4C8BE20 |
| |
| #define mmPDMA0_CORE_L2H_CMPR_HI 0x4C8BE24 |
| |
| #define mmPDMA0_CORE_L2H_MASK_LO 0x4C8BE28 |
| |
| #define mmPDMA0_CORE_L2H_MASK_HI 0x4C8BE2C |
| |
| #define mmPDMA0_CORE_IDLE_IND_MASK 0x4C8BE30 |
| |
| #define mmPDMA0_CORE_APB_ENABLER 0x4C8BE34 |
| |
| #endif /* ASIC_REG_PDMA0_CORE_REGS_H_ */ |