| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NVIDIA Tegra Display Serial Interface |
| |
| maintainers: |
| - Thierry Reding <thierry.reding@gmail.com> |
| - Jon Hunter <jonathanh@nvidia.com> |
| |
| properties: |
| compatible: |
| oneOf: |
| - enum: |
| - nvidia,tegra20-dsi |
| - nvidia,tegra30-dsi |
| - nvidia,tegra114-dsi |
| - nvidia,tegra124-dsi |
| - nvidia,tegra210-dsi |
| - nvidia,tegra186-dsi |
| |
| - items: |
| - const: nvidia,tegra132-dsi |
| - const: nvidia,tegra124-dsi |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: |
| minItems: 2 |
| maxItems: 3 |
| |
| clock-names: |
| minItems: 2 |
| maxItems: 3 |
| |
| resets: |
| items: |
| - description: module reset |
| |
| reset-names: |
| items: |
| - const: dsi |
| |
| operating-points-v2: true |
| |
| power-domains: |
| maxItems: 1 |
| |
| avdd-dsi-csi-supply: |
| description: phandle of a supply that powers the DSI controller |
| |
| nvidia,mipi-calibrate: |
| description: Should contain a phandle and a specifier specifying |
| which pads are used by this DSI output and need to be |
| calibrated. See nvidia,tegra114-mipi.yaml for details. |
| $ref: /schemas/types.yaml#/definitions/phandle-array |
| |
| nvidia,ddc-i2c-bus: |
| description: phandle of an I2C controller used for DDC EDID |
| probing |
| $ref: /schemas/types.yaml#/definitions/phandle |
| |
| nvidia,hpd-gpio: |
| description: specifies a GPIO used for hotplug detection |
| maxItems: 1 |
| |
| nvidia,edid: |
| description: supplies a binary EDID blob |
| $ref: /schemas/types.yaml#/definitions/uint8-array |
| |
| nvidia,panel: |
| description: phandle of a display panel |
| $ref: /schemas/types.yaml#/definitions/phandle |
| |
| nvidia,ganged-mode: |
| description: contains a phandle to a second DSI controller to |
| gang up with in order to support up to 8 data lanes |
| $ref: /schemas/types.yaml#/definitions/phandle |
| |
| allOf: |
| - $ref: ../dsi-controller.yaml# |
| - if: |
| properties: |
| compatible: |
| contains: |
| enum: |
| - nvidia,tegra20-dsi |
| - nvidia,tegra30-dsi |
| then: |
| properties: |
| clocks: |
| items: |
| - description: DSI module clock |
| - description: input for the pixel clock |
| |
| clock-names: |
| items: |
| - const: dsi |
| - const: parent |
| else: |
| properties: |
| clocks: |
| items: |
| - description: DSI module clock |
| - description: low-power module clock |
| - description: input for the pixel clock |
| |
| clock-names: |
| items: |
| - const: dsi |
| - const: lp |
| - const: parent |
| |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: nvidia,tegra186-dsi |
| then: |
| required: |
| - interrupts |
| |
| unevaluatedProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - resets |
| - reset-names |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/tegra186-clock.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/tegra186-powergate.h> |
| #include <dt-bindings/reset/tegra186-reset.h> |
| |
| dsi@15300000 { |
| compatible = "nvidia,tegra186-dsi"; |
| reg = <0x15300000 0x10000>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DSI>, |
| <&bpmp TEGRA186_CLK_DSIA_LP>, |
| <&bpmp TEGRA186_CLK_PLLD>; |
| clock-names = "dsi", "lp", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DSI>; |
| reset-names = "dsi"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| }; |