Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR3 SDRAM compliant to JEDEC JESD209-3

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

allOf:
  - $ref: jedec,lpddr-props.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - samsung,K3QF2F20DB
          - const: jedec,lpddr3
      - items:
          - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
          - const: jedec,lpddr3

  '#address-cells':
    const: 1
    deprecated: true

  manufacturer-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Manufacturer ID value read from Mode Register 5.  The property is
      deprecated, manufacturer should be derived from the compatible.
    deprecated: true

  '#size-cells':
    const: 0
    deprecated: true

  tCKE-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
      of clock cycles.

  tCKESR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      CKE minimum pulse width during SELF REFRESH (low pulse width during
      SELF REFRESH) in terms of number of clock cycles.

  tDQSCK-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      DQS output data access time from CK_t/CK_c in terms of number of clock
      cycles.

  tFAW-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 63
    description: |
      Four-bank activate window in terms of number of clock cycles.

  tMRD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Mode register set command delay in terms of number of clock cycles.

  tR2R-C2C-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      Additional READ-to-READ delay in chip-to-chip cases in terms of number
      of clock cycles.

  tRAS-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 63
    description: |
      Row active time in terms of number of clock cycles.

  tRC-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 63
    description: |
      ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.

  tRCD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      RAS-to-CAS delay in terms of number of clock cycles.

  tRFC-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 255
    description: |
      Refresh Cycle time in terms of number of clock cycles.

  tRL-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
     READ data latency in terms of number of clock cycles.

  tRPab-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Row precharge time (all banks) in terms of number of clock cycles.

  tRPpb-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Row precharge time (single banks) in terms of number of clock cycles.

  tRRD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Active bank A to active bank B in terms of number of clock cycles.

  tRTP-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Internal READ to PRECHARGE command delay in terms of number of clock
      cycles.

  tW2W-C2C-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
      of clock cycles.

  tWL-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      WRITE data latency in terms of number of clock cycles.

  tWR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      WRITE recovery time in terms of number of clock cycles.

  tWTR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Internal WRITE-to-READ command delay in terms of number of clock cycles.

  tXP-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 255
    description: |
      Exit power-down to next valid command delay in terms of number of clock
      cycles.

  tXSR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 1023
    description: |
      SELF REFRESH exit to next valid command delay in terms of number of clock
      cycles.

patternProperties:
  "^timings((-[0-9])+|(@[0-9a-f]+))?$":
    $ref: jedec,lpddr3-timings.yaml
    description: |
      The lpddr3 node may have one or more child nodes with timings.
      Each timing node provides AC timing parameters of the device for a given
      speed-bin. The user may provide the timings for as many speed-bins as is
      required.

required:
  - compatible
  - density
  - io-width

unevaluatedProperties: false

examples:
  - |
    lpddr3 {
        compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
        density = <16384>;
        io-width = <32>;

        tCKE-min-tck = <2>;
        tCKESR-min-tck = <2>;
        tDQSCK-min-tck = <5>;
        tFAW-min-tck = <5>;
        tMRD-min-tck = <5>;
        tR2R-C2C-min-tck = <0>;
        tRAS-min-tck = <5>;
        tRC-min-tck = <6>;
        tRCD-min-tck = <3>;
        tRFC-min-tck = <17>;
        tRL-min-tck = <14>;
        tRPab-min-tck = <2>;
        tRPpb-min-tck = <2>;
        tRRD-min-tck = <2>;
        tRTP-min-tck = <2>;
        tW2W-C2C-min-tck = <0>;
        tWL-min-tck = <8>;
        tWR-min-tck = <7>;
        tWTR-min-tck = <2>;
        tXP-min-tck = <2>;
        tXSR-min-tck = <12>;

        timings {
            compatible = "jedec,lpddr3-timings";
            max-freq = <800000000>;
            min-freq = <100000000>;
            tCKE = <3750>;
            tCKESR = <3750>;
            tFAW = <25000>;
            tMRD = <7000>;
            tR2R-C2C = <0>;
            tRAS = <23000>;
            tRC = <33750>;
            tRCD = <10000>;
            tRFC = <65000>;
            tRPab = <12000>;
            tRPpb = <12000>;
            tRRD = <6000>;
            tRTP = <3750>;
            tW2W-C2C = <0>;
            tWR = <7500>;
            tWTR = <3750>;
            tXP = <3750>;
            tXSR = <70000>;
        };
    };