Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX6 PCIe host controller

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>
  - Richard Zhu <hongxing.zhu@nxp.com>

description: |+
  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
  The controller instances are dual mode where in they can work either in
  Root Port mode or Endpoint mode but one at a time.

  See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
  bindings.

properties:
  compatible:
    enum:
      - fsl,imx6q-pcie
      - fsl,imx6sx-pcie
      - fsl,imx6qp-pcie
      - fsl,imx7d-pcie
      - fsl,imx8mq-pcie
      - fsl,imx8mm-pcie
      - fsl,imx8mp-pcie
      - fsl,imx95-pcie

  clocks:
    minItems: 3
    items:
      - description: PCIe bridge clock.
      - description: PCIe bus clock.
      - description: PCIe PHY clock.
      - description: Additional required clock entry for imx6sx-pcie,
           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.

  clock-names:
    minItems: 3
    maxItems: 4

  interrupts:
    items:
      - description: builtin MSI controller.

  interrupt-names:
    items:
      - const: msi

  reset-gpio:
    description: Should specify the GPIO for controlling the PCI bus device
      reset signal. It's not polarity aware and defaults to active-low reset
      sequence (L=reset state, H=operation state) (optional required).

  reset-gpio-active-high:
    description: If present then the reset sequence using the GPIO
      specified in the "reset-gpio" property is reversed (H=reset state,
      L=operation state) (optional required).
    type: boolean

required:
  - compatible
  - reg
  - reg-names
  - "#address-cells"
  - "#size-cells"
  - device_type
  - bus-range
  - ranges
  - interrupts
  - interrupt-names
  - "#interrupt-cells"
  - interrupt-map-mask
  - interrupt-map

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#
  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
  - if:
      properties:
        compatible:
          enum:
            - fsl,imx6q-pcie
            - fsl,imx6sx-pcie
            - fsl,imx6qp-pcie
            - fsl,imx7d-pcie
            - fsl,imx8mq-pcie
            - fsl,imx8mm-pcie
            - fsl,imx8mp-pcie
    then:
      properties:
        reg:
          maxItems: 2
        reg-names:
          items:
            - const: dbi
            - const: config

  - if:
      properties:
        compatible:
          enum:
            - fsl,imx95-pcie
    then:
      properties:
        reg:
          minItems: 4
          maxItems: 4
        reg-names:
          items:
            - const: dbi
            - const: config
            - const: atu
            - const: app

  - if:
      properties:
        compatible:
          enum:
            - fsl,imx6sx-pcie
    then:
      properties:
        clocks:
          minItems: 4
        clock-names:
          items:
            - const: pcie
            - const: pcie_bus
            - const: pcie_phy
            - const: pcie_inbound_axi

  - if:
      properties:
        compatible:
          enum:
            - fsl,imx8mq-pcie
            - fsl,imx95-pcie
    then:
      properties:
        clocks:
          minItems: 4
        clock-names:
          items:
            - const: pcie
            - const: pcie_bus
            - const: pcie_phy
            - const: pcie_aux

  - if:
      properties:
        compatible:
          enum:
            - fsl,imx6q-pcie
            - fsl,imx6qp-pcie
            - fsl,imx7d-pcie
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: pcie
            - const: pcie_bus
            - const: pcie_phy

  - if:
      properties:
        compatible:
          enum:
            - fsl,imx8mm-pcie
            - fsl,imx8mp-pcie
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: pcie
            - const: pcie_bus
            - const: pcie_aux

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie: pcie@1ffc000 {
        compatible = "fsl,imx6q-pcie";
        reg = <0x01ffc000 0x04000>,
              <0x01f00000 0x80000>;
        reg-names = "dbi", "config";
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        bus-range = <0x00 0xff>;
        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
        num-lanes = <1>;
        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi";
        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0x7>;
        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
                <&clks IMX6QDL_CLK_LVDS1_GATE>,
                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
        clock-names = "pcie", "pcie_bus", "pcie_phy";
    };
...