| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_NIC4_QM0_REGS_H_ |
| #define ASIC_REG_NIC4_QM0_REGS_H_ |
| |
| /* |
| ***************************************** |
| * NIC4_QM0 (Prototype: QMAN) |
| ***************************************** |
| */ |
| |
| #define mmNIC4_QM0_GLBL_CFG0 0xDE0000 |
| |
| #define mmNIC4_QM0_GLBL_CFG1 0xDE0004 |
| |
| #define mmNIC4_QM0_GLBL_PROT 0xDE0008 |
| |
| #define mmNIC4_QM0_GLBL_ERR_CFG 0xDE000C |
| |
| #define mmNIC4_QM0_GLBL_SECURE_PROPS_0 0xDE0010 |
| |
| #define mmNIC4_QM0_GLBL_SECURE_PROPS_1 0xDE0014 |
| |
| #define mmNIC4_QM0_GLBL_SECURE_PROPS_2 0xDE0018 |
| |
| #define mmNIC4_QM0_GLBL_SECURE_PROPS_3 0xDE001C |
| |
| #define mmNIC4_QM0_GLBL_SECURE_PROPS_4 0xDE0020 |
| |
| #define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_0 0xDE0024 |
| |
| #define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_1 0xDE0028 |
| |
| #define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_2 0xDE002C |
| |
| #define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_3 0xDE0030 |
| |
| #define mmNIC4_QM0_GLBL_NON_SECURE_PROPS_4 0xDE0034 |
| |
| #define mmNIC4_QM0_GLBL_STS0 0xDE0038 |
| |
| #define mmNIC4_QM0_GLBL_STS1_0 0xDE0040 |
| |
| #define mmNIC4_QM0_GLBL_STS1_1 0xDE0044 |
| |
| #define mmNIC4_QM0_GLBL_STS1_2 0xDE0048 |
| |
| #define mmNIC4_QM0_GLBL_STS1_3 0xDE004C |
| |
| #define mmNIC4_QM0_GLBL_STS1_4 0xDE0050 |
| |
| #define mmNIC4_QM0_GLBL_MSG_EN_0 0xDE0054 |
| |
| #define mmNIC4_QM0_GLBL_MSG_EN_1 0xDE0058 |
| |
| #define mmNIC4_QM0_GLBL_MSG_EN_2 0xDE005C |
| |
| #define mmNIC4_QM0_GLBL_MSG_EN_3 0xDE0060 |
| |
| #define mmNIC4_QM0_GLBL_MSG_EN_4 0xDE0068 |
| |
| #define mmNIC4_QM0_PQ_BASE_LO_0 0xDE0070 |
| |
| #define mmNIC4_QM0_PQ_BASE_LO_1 0xDE0074 |
| |
| #define mmNIC4_QM0_PQ_BASE_LO_2 0xDE0078 |
| |
| #define mmNIC4_QM0_PQ_BASE_LO_3 0xDE007C |
| |
| #define mmNIC4_QM0_PQ_BASE_HI_0 0xDE0080 |
| |
| #define mmNIC4_QM0_PQ_BASE_HI_1 0xDE0084 |
| |
| #define mmNIC4_QM0_PQ_BASE_HI_2 0xDE0088 |
| |
| #define mmNIC4_QM0_PQ_BASE_HI_3 0xDE008C |
| |
| #define mmNIC4_QM0_PQ_SIZE_0 0xDE0090 |
| |
| #define mmNIC4_QM0_PQ_SIZE_1 0xDE0094 |
| |
| #define mmNIC4_QM0_PQ_SIZE_2 0xDE0098 |
| |
| #define mmNIC4_QM0_PQ_SIZE_3 0xDE009C |
| |
| #define mmNIC4_QM0_PQ_PI_0 0xDE00A0 |
| |
| #define mmNIC4_QM0_PQ_PI_1 0xDE00A4 |
| |
| #define mmNIC4_QM0_PQ_PI_2 0xDE00A8 |
| |
| #define mmNIC4_QM0_PQ_PI_3 0xDE00AC |
| |
| #define mmNIC4_QM0_PQ_CI_0 0xDE00B0 |
| |
| #define mmNIC4_QM0_PQ_CI_1 0xDE00B4 |
| |
| #define mmNIC4_QM0_PQ_CI_2 0xDE00B8 |
| |
| #define mmNIC4_QM0_PQ_CI_3 0xDE00BC |
| |
| #define mmNIC4_QM0_PQ_CFG0_0 0xDE00C0 |
| |
| #define mmNIC4_QM0_PQ_CFG0_1 0xDE00C4 |
| |
| #define mmNIC4_QM0_PQ_CFG0_2 0xDE00C8 |
| |
| #define mmNIC4_QM0_PQ_CFG0_3 0xDE00CC |
| |
| #define mmNIC4_QM0_PQ_CFG1_0 0xDE00D0 |
| |
| #define mmNIC4_QM0_PQ_CFG1_1 0xDE00D4 |
| |
| #define mmNIC4_QM0_PQ_CFG1_2 0xDE00D8 |
| |
| #define mmNIC4_QM0_PQ_CFG1_3 0xDE00DC |
| |
| #define mmNIC4_QM0_PQ_ARUSER_31_11_0 0xDE00E0 |
| |
| #define mmNIC4_QM0_PQ_ARUSER_31_11_1 0xDE00E4 |
| |
| #define mmNIC4_QM0_PQ_ARUSER_31_11_2 0xDE00E8 |
| |
| #define mmNIC4_QM0_PQ_ARUSER_31_11_3 0xDE00EC |
| |
| #define mmNIC4_QM0_PQ_STS0_0 0xDE00F0 |
| |
| #define mmNIC4_QM0_PQ_STS0_1 0xDE00F4 |
| |
| #define mmNIC4_QM0_PQ_STS0_2 0xDE00F8 |
| |
| #define mmNIC4_QM0_PQ_STS0_3 0xDE00FC |
| |
| #define mmNIC4_QM0_PQ_STS1_0 0xDE0100 |
| |
| #define mmNIC4_QM0_PQ_STS1_1 0xDE0104 |
| |
| #define mmNIC4_QM0_PQ_STS1_2 0xDE0108 |
| |
| #define mmNIC4_QM0_PQ_STS1_3 0xDE010C |
| |
| #define mmNIC4_QM0_CQ_CFG0_0 0xDE0110 |
| |
| #define mmNIC4_QM0_CQ_CFG0_1 0xDE0114 |
| |
| #define mmNIC4_QM0_CQ_CFG0_2 0xDE0118 |
| |
| #define mmNIC4_QM0_CQ_CFG0_3 0xDE011C |
| |
| #define mmNIC4_QM0_CQ_CFG0_4 0xDE0120 |
| |
| #define mmNIC4_QM0_CQ_CFG1_0 0xDE0124 |
| |
| #define mmNIC4_QM0_CQ_CFG1_1 0xDE0128 |
| |
| #define mmNIC4_QM0_CQ_CFG1_2 0xDE012C |
| |
| #define mmNIC4_QM0_CQ_CFG1_3 0xDE0130 |
| |
| #define mmNIC4_QM0_CQ_CFG1_4 0xDE0134 |
| |
| #define mmNIC4_QM0_CQ_ARUSER_31_11_0 0xDE0138 |
| |
| #define mmNIC4_QM0_CQ_ARUSER_31_11_1 0xDE013C |
| |
| #define mmNIC4_QM0_CQ_ARUSER_31_11_2 0xDE0140 |
| |
| #define mmNIC4_QM0_CQ_ARUSER_31_11_3 0xDE0144 |
| |
| #define mmNIC4_QM0_CQ_ARUSER_31_11_4 0xDE0148 |
| |
| #define mmNIC4_QM0_CQ_STS0_0 0xDE014C |
| |
| #define mmNIC4_QM0_CQ_STS0_1 0xDE0150 |
| |
| #define mmNIC4_QM0_CQ_STS0_2 0xDE0154 |
| |
| #define mmNIC4_QM0_CQ_STS0_3 0xDE0158 |
| |
| #define mmNIC4_QM0_CQ_STS0_4 0xDE015C |
| |
| #define mmNIC4_QM0_CQ_STS1_0 0xDE0160 |
| |
| #define mmNIC4_QM0_CQ_STS1_1 0xDE0164 |
| |
| #define mmNIC4_QM0_CQ_STS1_2 0xDE0168 |
| |
| #define mmNIC4_QM0_CQ_STS1_3 0xDE016C |
| |
| #define mmNIC4_QM0_CQ_STS1_4 0xDE0170 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_0 0xDE0174 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_0 0xDE0178 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_0 0xDE017C |
| |
| #define mmNIC4_QM0_CQ_CTL_0 0xDE0180 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_1 0xDE0184 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_1 0xDE0188 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_1 0xDE018C |
| |
| #define mmNIC4_QM0_CQ_CTL_1 0xDE0190 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_2 0xDE0194 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_2 0xDE0198 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_2 0xDE019C |
| |
| #define mmNIC4_QM0_CQ_CTL_2 0xDE01A0 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_3 0xDE01A4 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_3 0xDE01A8 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_3 0xDE01AC |
| |
| #define mmNIC4_QM0_CQ_CTL_3 0xDE01B0 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_4 0xDE01B4 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_4 0xDE01B8 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_4 0xDE01BC |
| |
| #define mmNIC4_QM0_CQ_CTL_4 0xDE01C0 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_STS_0 0xDE01C4 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_STS_1 0xDE01C8 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_STS_2 0xDE01CC |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_STS_3 0xDE01D0 |
| |
| #define mmNIC4_QM0_CQ_PTR_LO_STS_4 0xDE01D4 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_STS_0 0xDE01D8 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_STS_1 0xDE01DC |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_STS_2 0xDE01E0 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_STS_3 0xDE01E4 |
| |
| #define mmNIC4_QM0_CQ_PTR_HI_STS_4 0xDE01E8 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_STS_0 0xDE01EC |
| |
| #define mmNIC4_QM0_CQ_TSIZE_STS_1 0xDE01F0 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_STS_2 0xDE01F4 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_STS_3 0xDE01F8 |
| |
| #define mmNIC4_QM0_CQ_TSIZE_STS_4 0xDE01FC |
| |
| #define mmNIC4_QM0_CQ_CTL_STS_0 0xDE0200 |
| |
| #define mmNIC4_QM0_CQ_CTL_STS_1 0xDE0204 |
| |
| #define mmNIC4_QM0_CQ_CTL_STS_2 0xDE0208 |
| |
| #define mmNIC4_QM0_CQ_CTL_STS_3 0xDE020C |
| |
| #define mmNIC4_QM0_CQ_CTL_STS_4 0xDE0210 |
| |
| #define mmNIC4_QM0_CQ_IFIFO_CNT_0 0xDE0214 |
| |
| #define mmNIC4_QM0_CQ_IFIFO_CNT_1 0xDE0218 |
| |
| #define mmNIC4_QM0_CQ_IFIFO_CNT_2 0xDE021C |
| |
| #define mmNIC4_QM0_CQ_IFIFO_CNT_3 0xDE0220 |
| |
| #define mmNIC4_QM0_CQ_IFIFO_CNT_4 0xDE0224 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_0 0xDE0228 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_1 0xDE022C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_2 0xDE0230 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_3 0xDE0234 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_LO_4 0xDE0238 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_0 0xDE023C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_1 0xDE0240 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_2 0xDE0244 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_3 0xDE0248 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE0_ADDR_HI_4 0xDE024C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_0 0xDE0250 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_1 0xDE0254 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_2 0xDE0258 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_3 0xDE025C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_LO_4 0xDE0260 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_0 0xDE0264 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_1 0xDE0268 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_2 0xDE026C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_3 0xDE0270 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE1_ADDR_HI_4 0xDE0274 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_0 0xDE0278 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_1 0xDE027C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_2 0xDE0280 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_3 0xDE0284 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_LO_4 0xDE0288 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_0 0xDE028C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_1 0xDE0290 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_2 0xDE0294 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_3 0xDE0298 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE2_ADDR_HI_4 0xDE029C |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_0 0xDE02A0 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_1 0xDE02A4 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_2 0xDE02A8 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_3 0xDE02AC |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_LO_4 0xDE02B0 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_0 0xDE02B4 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_1 0xDE02B8 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_2 0xDE02BC |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_3 0xDE02C0 |
| |
| #define mmNIC4_QM0_CP_MSG_BASE3_ADDR_HI_4 0xDE02C4 |
| |
| #define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_0 0xDE02C8 |
| |
| #define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_1 0xDE02CC |
| |
| #define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_2 0xDE02D0 |
| |
| #define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_3 0xDE02D4 |
| |
| #define mmNIC4_QM0_CP_LDMA_TSIZE_OFFSET_4 0xDE02D8 |
| |
| #define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE02E0 |
| |
| #define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE02E4 |
| |
| #define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE02E8 |
| |
| #define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE02EC |
| |
| #define mmNIC4_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE02F0 |
| |
| #define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE02F4 |
| |
| #define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE02F8 |
| |
| #define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE02FC |
| |
| #define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE0300 |
| |
| #define mmNIC4_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE0304 |
| |
| #define mmNIC4_QM0_CP_FENCE0_RDATA_0 0xDE0308 |
| |
| #define mmNIC4_QM0_CP_FENCE0_RDATA_1 0xDE030C |
| |
| #define mmNIC4_QM0_CP_FENCE0_RDATA_2 0xDE0310 |
| |
| #define mmNIC4_QM0_CP_FENCE0_RDATA_3 0xDE0314 |
| |
| #define mmNIC4_QM0_CP_FENCE0_RDATA_4 0xDE0318 |
| |
| #define mmNIC4_QM0_CP_FENCE1_RDATA_0 0xDE031C |
| |
| #define mmNIC4_QM0_CP_FENCE1_RDATA_1 0xDE0320 |
| |
| #define mmNIC4_QM0_CP_FENCE1_RDATA_2 0xDE0324 |
| |
| #define mmNIC4_QM0_CP_FENCE1_RDATA_3 0xDE0328 |
| |
| #define mmNIC4_QM0_CP_FENCE1_RDATA_4 0xDE032C |
| |
| #define mmNIC4_QM0_CP_FENCE2_RDATA_0 0xDE0330 |
| |
| #define mmNIC4_QM0_CP_FENCE2_RDATA_1 0xDE0334 |
| |
| #define mmNIC4_QM0_CP_FENCE2_RDATA_2 0xDE0338 |
| |
| #define mmNIC4_QM0_CP_FENCE2_RDATA_3 0xDE033C |
| |
| #define mmNIC4_QM0_CP_FENCE2_RDATA_4 0xDE0340 |
| |
| #define mmNIC4_QM0_CP_FENCE3_RDATA_0 0xDE0344 |
| |
| #define mmNIC4_QM0_CP_FENCE3_RDATA_1 0xDE0348 |
| |
| #define mmNIC4_QM0_CP_FENCE3_RDATA_2 0xDE034C |
| |
| #define mmNIC4_QM0_CP_FENCE3_RDATA_3 0xDE0350 |
| |
| #define mmNIC4_QM0_CP_FENCE3_RDATA_4 0xDE0354 |
| |
| #define mmNIC4_QM0_CP_FENCE0_CNT_0 0xDE0358 |
| |
| #define mmNIC4_QM0_CP_FENCE0_CNT_1 0xDE035C |
| |
| #define mmNIC4_QM0_CP_FENCE0_CNT_2 0xDE0360 |
| |
| #define mmNIC4_QM0_CP_FENCE0_CNT_3 0xDE0364 |
| |
| #define mmNIC4_QM0_CP_FENCE0_CNT_4 0xDE0368 |
| |
| #define mmNIC4_QM0_CP_FENCE1_CNT_0 0xDE036C |
| |
| #define mmNIC4_QM0_CP_FENCE1_CNT_1 0xDE0370 |
| |
| #define mmNIC4_QM0_CP_FENCE1_CNT_2 0xDE0374 |
| |
| #define mmNIC4_QM0_CP_FENCE1_CNT_3 0xDE0378 |
| |
| #define mmNIC4_QM0_CP_FENCE1_CNT_4 0xDE037C |
| |
| #define mmNIC4_QM0_CP_FENCE2_CNT_0 0xDE0380 |
| |
| #define mmNIC4_QM0_CP_FENCE2_CNT_1 0xDE0384 |
| |
| #define mmNIC4_QM0_CP_FENCE2_CNT_2 0xDE0388 |
| |
| #define mmNIC4_QM0_CP_FENCE2_CNT_3 0xDE038C |
| |
| #define mmNIC4_QM0_CP_FENCE2_CNT_4 0xDE0390 |
| |
| #define mmNIC4_QM0_CP_FENCE3_CNT_0 0xDE0394 |
| |
| #define mmNIC4_QM0_CP_FENCE3_CNT_1 0xDE0398 |
| |
| #define mmNIC4_QM0_CP_FENCE3_CNT_2 0xDE039C |
| |
| #define mmNIC4_QM0_CP_FENCE3_CNT_3 0xDE03A0 |
| |
| #define mmNIC4_QM0_CP_FENCE3_CNT_4 0xDE03A4 |
| |
| #define mmNIC4_QM0_CP_STS_0 0xDE03A8 |
| |
| #define mmNIC4_QM0_CP_STS_1 0xDE03AC |
| |
| #define mmNIC4_QM0_CP_STS_2 0xDE03B0 |
| |
| #define mmNIC4_QM0_CP_STS_3 0xDE03B4 |
| |
| #define mmNIC4_QM0_CP_STS_4 0xDE03B8 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_LO_0 0xDE03BC |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_LO_1 0xDE03C0 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_LO_2 0xDE03C4 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_LO_3 0xDE03C8 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_LO_4 0xDE03CC |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_HI_0 0xDE03D0 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_HI_1 0xDE03D4 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_HI_2 0xDE03D8 |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_HI_3 0xDE03DC |
| |
| #define mmNIC4_QM0_CP_CURRENT_INST_HI_4 0xDE03E0 |
| |
| #define mmNIC4_QM0_CP_BARRIER_CFG_0 0xDE03F4 |
| |
| #define mmNIC4_QM0_CP_BARRIER_CFG_1 0xDE03F8 |
| |
| #define mmNIC4_QM0_CP_BARRIER_CFG_2 0xDE03FC |
| |
| #define mmNIC4_QM0_CP_BARRIER_CFG_3 0xDE0400 |
| |
| #define mmNIC4_QM0_CP_BARRIER_CFG_4 0xDE0404 |
| |
| #define mmNIC4_QM0_CP_DBG_0_0 0xDE0408 |
| |
| #define mmNIC4_QM0_CP_DBG_0_1 0xDE040C |
| |
| #define mmNIC4_QM0_CP_DBG_0_2 0xDE0410 |
| |
| #define mmNIC4_QM0_CP_DBG_0_3 0xDE0414 |
| |
| #define mmNIC4_QM0_CP_DBG_0_4 0xDE0418 |
| |
| #define mmNIC4_QM0_CP_ARUSER_31_11_0 0xDE041C |
| |
| #define mmNIC4_QM0_CP_ARUSER_31_11_1 0xDE0420 |
| |
| #define mmNIC4_QM0_CP_ARUSER_31_11_2 0xDE0424 |
| |
| #define mmNIC4_QM0_CP_ARUSER_31_11_3 0xDE0428 |
| |
| #define mmNIC4_QM0_CP_ARUSER_31_11_4 0xDE042C |
| |
| #define mmNIC4_QM0_CP_AWUSER_31_11_0 0xDE0430 |
| |
| #define mmNIC4_QM0_CP_AWUSER_31_11_1 0xDE0434 |
| |
| #define mmNIC4_QM0_CP_AWUSER_31_11_2 0xDE0438 |
| |
| #define mmNIC4_QM0_CP_AWUSER_31_11_3 0xDE043C |
| |
| #define mmNIC4_QM0_CP_AWUSER_31_11_4 0xDE0440 |
| |
| #define mmNIC4_QM0_ARB_CFG_0 0xDE0A00 |
| |
| #define mmNIC4_QM0_ARB_CHOISE_Q_PUSH 0xDE0A04 |
| |
| #define mmNIC4_QM0_ARB_WRR_WEIGHT_0 0xDE0A08 |
| |
| #define mmNIC4_QM0_ARB_WRR_WEIGHT_1 0xDE0A0C |
| |
| #define mmNIC4_QM0_ARB_WRR_WEIGHT_2 0xDE0A10 |
| |
| #define mmNIC4_QM0_ARB_WRR_WEIGHT_3 0xDE0A14 |
| |
| #define mmNIC4_QM0_ARB_CFG_1 0xDE0A18 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_0 0xDE0A20 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_1 0xDE0A24 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_2 0xDE0A28 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_3 0xDE0A2C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_4 0xDE0A30 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_5 0xDE0A34 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_6 0xDE0A38 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_7 0xDE0A3C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_8 0xDE0A40 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_9 0xDE0A44 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_10 0xDE0A48 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_11 0xDE0A4C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_12 0xDE0A50 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_13 0xDE0A54 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_14 0xDE0A58 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_15 0xDE0A5C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_16 0xDE0A60 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_17 0xDE0A64 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_18 0xDE0A68 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_19 0xDE0A6C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_20 0xDE0A70 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_21 0xDE0A74 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_22 0xDE0A78 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_23 0xDE0A7C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_24 0xDE0A80 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_25 0xDE0A84 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_26 0xDE0A88 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_27 0xDE0A8C |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_28 0xDE0A90 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_29 0xDE0A94 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_30 0xDE0A98 |
| |
| #define mmNIC4_QM0_ARB_MST_AVAIL_CRED_31 0xDE0A9C |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_INC 0xDE0AA0 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xDE0AA4 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xDE0AA8 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xDE0AAC |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xDE0AB0 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xDE0AB4 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xDE0AB8 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xDE0ABC |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xDE0AC0 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xDE0AC4 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xDE0AC8 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xDE0ACC |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xDE0AD0 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xDE0AD4 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xDE0AD8 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xDE0ADC |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xDE0AE0 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xDE0AE4 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xDE0AE8 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xDE0AEC |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xDE0AF0 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xDE0AF4 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xDE0AF8 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xDE0AFC |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xDE0B00 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xDE0B04 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xDE0B08 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xDE0B0C |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xDE0B10 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xDE0B14 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xDE0B18 |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xDE0B1C |
| |
| #define mmNIC4_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xDE0B20 |
| |
| #define mmNIC4_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xDE0B28 |
| |
| #define mmNIC4_QM0_ARB_MST_SLAVE_EN 0xDE0B2C |
| |
| #define mmNIC4_QM0_ARB_MST_QUIET_PER 0xDE0B34 |
| |
| #define mmNIC4_QM0_ARB_SLV_CHOISE_WDT 0xDE0B38 |
| |
| #define mmNIC4_QM0_ARB_SLV_ID 0xDE0B3C |
| |
| #define mmNIC4_QM0_ARB_MSG_MAX_INFLIGHT 0xDE0B44 |
| |
| #define mmNIC4_QM0_ARB_MSG_AWUSER_31_11 0xDE0B48 |
| |
| #define mmNIC4_QM0_ARB_MSG_AWUSER_SEC_PROP 0xDE0B4C |
| |
| #define mmNIC4_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE0B50 |
| |
| #define mmNIC4_QM0_ARB_BASE_LO 0xDE0B54 |
| |
| #define mmNIC4_QM0_ARB_BASE_HI 0xDE0B58 |
| |
| #define mmNIC4_QM0_ARB_STATE_STS 0xDE0B80 |
| |
| #define mmNIC4_QM0_ARB_CHOISE_FULLNESS_STS 0xDE0B84 |
| |
| #define mmNIC4_QM0_ARB_MSG_STS 0xDE0B88 |
| |
| #define mmNIC4_QM0_ARB_SLV_CHOISE_Q_HEAD 0xDE0B8C |
| |
| #define mmNIC4_QM0_ARB_ERR_CAUSE 0xDE0B9C |
| |
| #define mmNIC4_QM0_ARB_ERR_MSG_EN 0xDE0BA0 |
| |
| #define mmNIC4_QM0_ARB_ERR_STS_DRP 0xDE0BA8 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_0 0xDE0BB0 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_1 0xDE0BB4 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_2 0xDE0BB8 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_3 0xDE0BBC |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_4 0xDE0BC0 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_5 0xDE0BC4 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_6 0xDE0BC8 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_7 0xDE0BCC |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_8 0xDE0BD0 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_9 0xDE0BD4 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_10 0xDE0BD8 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_11 0xDE0BDC |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_12 0xDE0BE0 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_13 0xDE0BE4 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_14 0xDE0BE8 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_15 0xDE0BEC |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_16 0xDE0BF0 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_17 0xDE0BF4 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_18 0xDE0BF8 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_19 0xDE0BFC |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_20 0xDE0C00 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_21 0xDE0C04 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_22 0xDE0C08 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_23 0xDE0C0C |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_24 0xDE0C10 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_25 0xDE0C14 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_26 0xDE0C18 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_27 0xDE0C1C |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_28 0xDE0C20 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_29 0xDE0C24 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_30 0xDE0C28 |
| |
| #define mmNIC4_QM0_ARB_MST_CRED_STS_31 0xDE0C2C |
| |
| #define mmNIC4_QM0_CGM_CFG 0xDE0C70 |
| |
| #define mmNIC4_QM0_CGM_STS 0xDE0C74 |
| |
| #define mmNIC4_QM0_CGM_CFG1 0xDE0C78 |
| |
| #define mmNIC4_QM0_LOCAL_RANGE_BASE 0xDE0C80 |
| |
| #define mmNIC4_QM0_LOCAL_RANGE_SIZE 0xDE0C84 |
| |
| #define mmNIC4_QM0_CSMR_STRICT_PRIO_CFG 0xDE0C90 |
| |
| #define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_1 0xDE0C94 |
| |
| #define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_0 0xDE0C98 |
| |
| #define mmNIC4_QM0_LBW_WR_RATE_LIM_CFG_1 0xDE0C9C |
| |
| #define mmNIC4_QM0_HBW_RD_RATE_LIM_CFG_0 0xDE0CA0 |
| |
| #define mmNIC4_QM0_GLBL_AXCACHE 0xDE0CA4 |
| |
| #define mmNIC4_QM0_IND_GW_APB_CFG 0xDE0CB0 |
| |
| #define mmNIC4_QM0_IND_GW_APB_WDATA 0xDE0CB4 |
| |
| #define mmNIC4_QM0_IND_GW_APB_RDATA 0xDE0CB8 |
| |
| #define mmNIC4_QM0_IND_GW_APB_STATUS 0xDE0CBC |
| |
| #define mmNIC4_QM0_GLBL_ERR_ADDR_LO 0xDE0CD0 |
| |
| #define mmNIC4_QM0_GLBL_ERR_ADDR_HI 0xDE0CD4 |
| |
| #define mmNIC4_QM0_GLBL_ERR_WDATA 0xDE0CD8 |
| |
| #define mmNIC4_QM0_GLBL_MEM_INIT_BUSY 0xDE0D00 |
| |
| #endif /* ASIC_REG_NIC4_QM0_REGS_H_ */ |
